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AD4080BBCZ データシート(PDF) 71 Page - Analog Devices

部品番号 AD4080BBCZ
部品情報  20-Bit, 40 MSPS, Differential SAR ADC
PDF  95 Pages
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メーカー  AD [Analog Devices]
ホームページ  http://www.analog.com
Logo AD - Analog Devices

AD4080BBCZ データシート(HTML) 71 Page - Analog Devices

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Data Sheet
AD4080
DIGITAL FEATURES
analog.com
Rev. 0 | 71 of 95
SYSTEM ERROR CORRECTION
COEFFICIENTS
Systematic gain and offset errors exist in all practical data acquis-
ition circuits, and thus, the need for correction is essential to
maximize the precision of the measurement channel. While these
quantities can be corrected for in the host processor, implementa-
tion can be inefficient and consume more power than if integrated
within the data converter. To minimize these challenges for the end
user, the AD4080 has integrated both gain and offset correction on
a per sample basis.
To describe the available error corrections, consider that the trans-
fer function of an ideal ADC can be described by the straight line
equation.
y = mx + c
(2)
This equation can be applied to the ADC transfer function where:
y is the corrected ADC result.
m is the gain or slope of the line.
x is the uncorrected ADC result.
c is the offset.
The gain or slop of the line can be described as follows:
m = (y2 − y1)/(x2 − x1)
where the following are in volts:
y2 is the input voltage at close to the positive full-scale input.
y1 is the input voltage at close to the negative full-scale input.
x2 is the converted voltage with the y2 voltage applied at the input.
x1 is the converted voltage with the y1 voltage applied at the input.
The ideal slope or gain is m = 1 V/V
The system error correction coefficients in the Offset Error Correc-
tion and Gain Error Correction sections detail how signal chain
errors in offset (c) and gain (m) can be corrected using the configu-
ration registers of the AD4080.
Offset Error Correction
The AD4080 is factory calibrated to give low zero error. To account
for system offset errors that may be present in a users application
signal chain, an offset error correction function was included, which
allows users to correct for system offsets in their application by
applying a code to the OFFSET bit field in the offset Register at
Address 0x24 and Address 0x25, Bits[11:0]. This bit field is a 12-bit
value in a twos compliment data format.
The bit field is a 12-bit value in a twos compliment data format and
OFFSET LSB represents the value of the ADC LSB as defined in
the Transfer Function section. The range of offset error correction is
therefore defined as −2048 × LSB (0x800) to +2047 × LSB (0x7FF).
This represents a voltage range of ±11.71 mV for the specified
VREFIN = 3.0 V. The default value for this register, after power on,
or after a software reset, is 0x000, which represents the zero offset
correction applied.
Gain Error Correction
The AD4080 is a high precision ADC with factory calibrated, gain
error correction. To allow a user to correct for any signal chain
gain error within their application, the GAIN register (see the Gain
Correction Register, Address 0x27 and Address 0x28) can be used.
The GAIN bit field is a 10-bit value that allows a nominal gain error
correction of ±1.5594% of full scale. The 10-bit register is coded in
a straight binary data format, where the default value after power
on, or software reset, is 0x200. This value represents no gain error
correction being applied to the ADC results.
With the GAIN register first set to the default 0x200 value, the user
can perform a two-point voltage measurement, preferably close
to positive and negative full-scale inputs, and use the slope or
gain equation in the System Error Correction Coefficients section
to determine their system gain error. This system error can then
be adjusted with a resolution of 1.5594%/512 = 0.00305%. The
required correction calculated can be input to the GAIN register.



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