AD4080BBCZ datasheet(75/95 Pages) AD

75 / 95 page

Data Sheet

AD4080

CONFIGURATION REGISTERS

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Rev. 0 | 75 of 95

Interface Configuration A Register

Address: 0x00, Reset: 0x10, Name: INTERFACE_CONFIG_A

Figure 108. Interface Configuration A Settings

Table 32. Bit Descriptions for INTERFACE_CONFIG_A

Bits

Bit Name

Description

Reset

Access

SW_RESET

First of the Two SW_RESET Bits. This bit appears in two locations in this register. Both locations must

be written to at the same time to trigger a software reset of the device. This action returns any previously

configured registers to their default settings, except for the ADDR_ASCENSION bit from the Interface

Configuration A Register, which keeps its previous value.

0x0

R/W

Only use this reset method once the ADC is in an idle state, where conversions are not being clocked, and

any existing conversions are completed.

RESERVED

Reserved. Write 0 to this bit.

0x0

ADDR_ASCENSION

Determines Sequential Addressing Behavior.

0x0

R/W

0: Address is decremented by one when streaming.

1: Address is Incremented by one when streaming.

SDO_ENABLE

SDO Pin Enable.

0x1

[3:1]

RESERVED

Reserved. Write 000 to these bits.

0x0

SW_RESETX

Second of the Two SW_RESET Bits. This bit appears in two locations in this register. Both locations must

be written to at the same time to trigger a software reset of the device. This action returns any previously

configured registers to their default settings, except for the ADDR_ASCENSION bitd from the Interface

Configuration A Register, which keeps its previous value.

0x0

R/W

Only use this reset method once the ADC is in an idle state, where conversions are not being clocked, and

any existing conversion are completed.

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