AD4080BBCZ datasheet(85/95 Pages) AD

85 / 95 page

Data Sheet

AD4080

CONFIGURATION REGISTERS

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Rev. 0 | 85 of 95

ADC Data Interface Configuration B Register

Address: 0x16, Reset: 0x00, Name: ADC_DATA_INTF_CONFIG_B

Figure 125. ADC Data Interface Configuration B Register

Table 49. Bit Descriptions for ADC_DATA_INTF_CONFIG_B

Bits

Bit Name

Description

Reset

Access

[7:4]

LVDS_CNV_CLK_CNT

LVDS Clock Data Capture. Determines the negative edge of the LVDS clock that the MSB of the

conversion result is available in during conversion mode. Refer to the ADC Result Latency and LVDS

Interface Alignment section of further information on setting this value.

0x0

R/W

LVDS_SELF_CLK_MODE

Enable/Disable LVDS Self Clock Mode.

0x0

R/W

0: Echo Clock Mode Enabled. LVDS DCO transmitter is powered up.

1: Self Clock Mode Enabled. LVDS DCO transmitter is powered down .

LVDS_MNC_EN

Enable LVDS Manchester Encoding. Manchester encoding is only applied for LVDS read during

conversion mode in dual lane mode. This mode only operates with FILTER_SEL = 0, digital filter

disabled.

0x0

R/W

0: Manchester Encoding Disabled.

1: Manchester Encoding Enabled.

RESERVED

Reserved. Write 0b0 to this bit.

0x0

LVDS_CNV_EN

Configure CNV in LVDS Mode. Only applicable when LVDS interface is selected.

0x0

R/W

0: CNV Pin Configured in CMOS Mode.

1: CNV Pin Configured in LVDS Mode.

ADC Data Interface Configuration C Register

Address: 0x17, Reset: 0x20, Name: ADC_DATA_INTF_CONFIG_C

Figure 126. ADC Data Interface Configuration C Register

Table 50. Bit Descriptions for ADC_DATA_INTF_CONFIG_C

Bits

Bit Name

Description

Reset

Access

LVDS_RX_CURRENT

LVDS Receivers Current Mode. 1'b0 − 1× current. 1'b1 − 2x current.

0x0

R/W

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