AD4080BBCZ datasheet(33/95 Pages) AD

33 / 95 page

Data Sheet

AD4080

DIGITAL INTERFACE

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Rev. 0 | 33 of 95

Table 14. Configuration Memory Controller Options Summary (Continued)

Interface Option

Description

Loop Count (LOOP_COUNT)

Sets the data byte count before looping to the start address. When streaming data, a nonzero value sets the number of data bytes written

before the address loops back to the start address. A maximum of 255 bytes can be written using this approach. A value of 0x00 disables

the loop back so that addressing wraps around at the upper and lower limits of the memory. After writing this register, the loop value applies

only to the following SPI instruction and auto clears upon the end of that instruction.

Instruction Phase

An instruction phase immediately follows the assertion of the CS

pin (Logic 0) and is terminated by transmission of a complete

instruction packet or deassertion of CS. The instruction packet

starts with a single command bit indicating the operation type (Logic

1 for read, and Logic 0 for write), which is then followed by the start

address for the operation. By default, the address is 15-bit long,

but the data interface has an optional short instruction mode, in

which, it is reduced to 7 bits. The short instruction mode is enabled

by setting the SHORT_INSTRUCTION bit = 1 in the Interface

Configuration B register (see the Interface Configuration B Register

section, Address 0x01).

Data Phase

Each instruction phase is immediately followed by an associated

data phase, during which data is either shifted out of the serial

data output (SDO) on the falling edge of SCLK (read access) or

is shifted into the device configuration memory through SDI on

the rising edge of SCLK (write access). The minimum size of the

data payload is defined as a single byte; however, it can include

multiple bytes depending on the depth of the register addressed

and the interface configuration settings for the SINGLE_INST and

STRICT_REGISTER_ACCESS bits (Register 0x01, Bit 7, and Reg-

ister 0x10, Bit 5, respectively.

Write Access

When CS is forced low, a new serial instruction phase begins.

The first bit sent in the instruction phase is the command bit, and

when it is forced low (Logic 0) this indicates a write operation. The

command bit is followed by an address that, for the write operation,

indicates where the information received in the subsequent data

phase will be stored. As previously described in the Instruction

Phase section, the address has a default length of 15 bits, but the

address can be optionally shortened to 7 bits.

Following the instruction phase, an integer number of bytes contain-

ing the data payload for one or more registers in the configuration

memory are transmitted to the AD4080. The size of the payload

in this data phase is bounded by the selected SINGLE_INST and

STRICT_REGISTER_ACCESS interface options as described in

the Strict Access Selection and Multibyte Registers section. Each

data byte is loaded into the addressed register as it is received,

assuming the interface CRC is disabled. If the CRC is enabled,

however, the addressed data register is only loaded if the internally

computed checksum matches the CRC value received from the

host. In the event that the computed CRC and received checksum

from the host for a given entity are inconsistent, the register update

terminates and all subsequent data in the given frame is treated

as invalid as well. The checksum computation for the interface

CRC function is described in detail in the Configuration Cyclical

Redundancy Check (CRC) section.

Note that, during the data phase of a write operation, the SDO

output is driven to Logic 0 when the product is not reporting the

latest CRC checksum to ensure a valid data state is presented to

the host controllers SDI pin.

Read Access

The SPI enables read access to the configuration registers to

validate previous configuration writes, read the device identification,

or verify the interface status.

When CS is forced low, a new serial instruction phase begins.

The first bit sent in the instruction phase is the command bit, and

when it is forced high (Logic 1) this indicates a read operation.

The command bit is followed by an address that, for the read

operation, indicates the start address for the register space to be

accessed. As previously described in the Instruction Phase section,

the address has a default length of 15 bits, but the address can be

optionally shortened to 7 bits.

During the subsequent data phase, content from the addressed

falling edge of SCLK. The number of bytes transmitted in any

one data frame is determined by the interface configuration set-

ting selections for the SHORT_INSTRUCTION and STRICT_REG-

ISTER_ACCESS options as demonstrated in the examples shown

in the Instruction Mode Selection section and the Strict Access

Selection and Multibyte Registers section.

Instruction Mode Selection

The configuration interface memory controller defaults to streaming

mode upon power up (SINGLE_INST = 0). In streaming mode, mul-

tiple, contiguous registers are accessed in a single SPI frame, start-

ing at the address specified in the instruction phase. In streaming

mode, only one instruction phase is permitted per SPI frame, requir-

ing a new SPI frame be initiated for changing access commands

or otherwise access a noncontiguous address in the register space.

For each byte transferred during the subsequent data phase, the

internal address counter is automatically updated according to the

setting of the ADDR_ASCENSION bit in the Interface Configuration

A register (see the Interface Configuration A Register section), in

the way specified by Table 15.

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