AD4080BBCZ datasheet(25/95 Pages) AD

25 / 95 page

Data Sheet

AD4080

THEORY OF OPERATION

analog.com

Rev. 0 | 25 of 95

(see the Device Configuration Register section) to update the

OPERATING_MODES bits.

Table 11. Power Saving Operating Modes

Operating

Mode

OPERATING_MODES

Bits Value

Description

Effect

Wake-Up Time (Maximum Time to

Normal Mode)

Normal

0b00

Normal operating mode

Normal operation.

Not applicable

Standby

0b01

Standby operating mode

The internal IOVDD LDO regulator is disabled.

100 μs

If IOVDD is not externally supplied, all GPIOx and all

LVDS data interface and SPI data interface signals

are disabled. For the SPI configuration interface only.

writes to the device configuration register (see the

Device Configuration Register section) and Interface

Configuration A register (see the Interface Configuration

A Register section) are allowed.

If IOVDD is externally supplied, all GPIOx and SPI data

interface signals are enabled. The SPI configuration

interface is fully enabled. Because the SPI data

interface remains enabled, the user can access data

in the result FIFO (see the Result FIFO section).

The ADC core is powered down. The analog circuitry

remains in reset (ANA_RESET remains asserted), and

no ADC conversions can be performed.

The VDD33 supply can be removed to reduce power.

When in use, the internal VDD11 LDO regulator remains

on.

The internal reference buffer is enabled.

Common-mode output buffer is enabled.

The LVDS interface is disabled.

Sleep

0b10

Low power operating mode

The internal IOVDD LDO regulator is disabled.

100 ms

If IOVDD is not externally supplied, all GPIOx and all

LVDS data interface and SPI data interface signals

are disabled. For the SPI configuration interface only,

writes to the device configuration register (see the

Device Configuration Register section) and Interface

Configuration A register (see the Interface Configuration

A Register section) are allowed.

If IOVDD is externally supplied, all GPIOx and SPI data

interface signals are enabled. The SPI configuration

interface is fully enabled. Because the SPI data

interface remains enabled, the user can access data

in the result FIFO (see the Result FIFO section).

The ADC core is powered down. The analog circuitry

remains in reset (ANA_RESET remains asserted), and

no ADC conversions can be performed.

The VDD33 supply can be removed to reduce power.

The internal reference buffer is disabled

When enabled, the internal VDD11 LDO regulator

remains on.

The common-mode output buffer is disabled.

The LVDS interface is disabled.

The SPI data interface remains enabled to access data

in the result FIFO (see the Result FIFO section).

AD4080BBCZ データシート(PDF) 25 Page - Analog Devices

AD4080BBCZ データシート(HTML) 25 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95

データシートダウンロード

リンク URL

AD4080BBCZ データシート(PDF) 25 Page - Analog Devices

AD4080BBCZ データシート(HTML) 25 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95

データシート ダウンロード

リンク URL

データシートダウンロード