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LAN9252/ML データシート(PDF) 266 Page - Microchip Technology |
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LAN9252/ML データシート(HTML) 266 Page - Microchip Technology |
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266 / 329 page  LAN9252 DS00001909A-page 266 2015 Microchip Technology Inc. 12.14.55 PHY DATA REGISTER Note 31: Write access depends upon the assignment of the MI interface (ECAT/PDI). Write access is generally blocked if the MII interface is busy (Busy bit of MII Management Control/Status Register = 1) Note: For EtherCAT Core CSR registers longer than one byte, the LSB has the lowest address and the MSB the highest address. 12.14.56 MII MANAGEMENT ECAT ACCESS STATE REGISTER Note 32: Write access only possible if the Access to MII Management (PDI) bit of the MII Management PDI Access State Register is 0. Offset: 0514h-0515h Size: 16 bits Bits Description ECAT Type PDI Type Default 15:0 PHY Read/Write Data R/W Note 31 R/W Note 31 0000h Offset: 0516h Size: 8 bits Bits Description ECAT Type PDI Type Default 7:1 RESERVED Write 0. RO RO 0000000b 0 Access to MII Management (ECAT) 0: ECAT enables PDI takeover of MII management control 1: ECAT claims exclusive access to MII management R/W Note 32 RO 0b |
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