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LAN9252/ML データシート(PDF) 290 Page - Microchip Technology |
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LAN9252/ML データシート(HTML) 290 Page - Microchip Technology |
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290 / 329 page  LAN9252 DS00001909A-page 290 2015 Microchip Technology Inc. 12.14.89 LATCH1 TIME POSITIVE EDGE REGISTER Note: Register bits [63:8] are internally latched (ECAT/PDI independently) when bits [7:0] are read, which guaran- tees reading a consistent value. Clearing the Event LATCH1 Positive Edge bit of the LATCH1 Status Reg- ister depends upon setting of the Latch In Unit 1 bit of the Cyclic Unit Control Register. Note: For EtherCAT Core CSR registers longer than one byte, the LSB has the lowest address and the MSB the highest address. 12.14.90 LATCH1 TIME NEGATIVE EDGE REGISTER Note: Register bits [63:8] are internally latched (ECAT/PDI independently) when bits [7:0] are read, which guaran- tees reading a consistent value. Clearing the Event LATCH1 Negative Edge bit of the LATCH1 Status Reg- ister depends upon setting of the Latch In Unit 1 bit of the Cyclic Unit Control Register. Note: For EtherCAT Core CSR registers longer than one byte, the LSB has the lowest address and the MSB the highest address. Offset: 09C0h-09C7h Size: 64 bits Bits Description ECAT Type PDI Type Default 63:0 This register captures the System Time at the positive edge of the LATCH1 signal. Note: Reading this register clears the Event LATCH1 Posi- tive Edge bit of the LATCH1 Status Register RO RO 00000000h 00000000h Offset: 09C8h-09CFh Size: 64 bits Bits Description ECAT Type PDI Type Default 63:0 This register captures the System Time at the negative edge of the LATCH1 signal. Note: Reading this register clears the Event LATCH1 Neg- ative Edge bit of the LATCH1 Status Register RO RO 00000000h 00000000h |
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