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DP83867CS データシート(PDF) 34 Page - Texas Instruments |
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DP83867CS データシート(HTML) 34 Page - Texas Instruments |
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34 / 129 page  Table 7-4. Loopback Availability (continued) LOOPBACK MODE MAC INTERFACE 1000M 100M 10M AVAILABILIT Y LINK STATUS AVAILABILIT Y LINK STATUS AVAILABILIT Y LINK STATUS Analog RGMII Yes Yes Yes Yes Yes Yes External RGMII No No Yes Yes Yes Yes MII SGMII Yes No Yes No No No Digital SGMII Yes Yes Yes Yes No No IO SGMII Yes Yes Yes Yes No No 7.4.4.1 Near-End Loopback Near-end loopback provides the ability to loop the transmitted data back to the receiver through the digital or analog circuitry. The point at which the signal is looped back is selected using loopback control bits with several options being provided. When configuring loopback modes, the Loopback Configuration Register (LOOPCR), address 0x00FE, can be set to 0xE720. To maintain the desired operating mode, Auto-Negotiation can be disabled before selecting the Near-End Loopback mode. This constraint does not apply for external-loopback mode. Auto-MDIX can be disabled before selecting the Near-End Loopback mode. MDI or MDIX configuration can be manually configured. 7.4.4.1.1 MII Loopback MII Loopback is the shallowest loop through the PHY. The configuration is a useful test mode to validate communications between the MAC and the PHY. While in MII Loopback mode the data is looped back, and can also be configured through register to transmit onto the media. 7.4.4.1.2 PCS Loopback PCS Loopback occurs in the PCS layer of the PHY. No signal processing is performed when using PCS Loopback. 7.4.4.1.3 Digital Loopback Digital Loopback includes the entire digital transmit – receive path. Data is looped back prior to the analog circuitry. 7.4.4.1.4 Analog Loopback Analog Loopback includes the entire analog transmit-receive path. 7.4.4.2 External Loopback When operating in 10BASE-Te or 100Base-T mode, signals can be looped back at the RJ-45 connector by wiring the transmit pins to the receive pins. Due to the nature of the signaling in 1000Base-T mode, this type of external loopback is not supported. Analog loopback provides a way to loop data back in the analog circuitry when operating in 1000Base-T mode. For proper operation in Analog Loopback mode, attach 100Ω terminations to the RJ45 connector. 7.4.4.3 Far-End (Reverse) Loopback Far-end (Reverse) Loopback is a special test mode to allow testing the PHY from the link-partner side. In this mode, data that is received from the link partner passes through the PHY's receiver, is looped back at the MAC interface and is transmitted back to the link partner. While in Reverse Loopback mode, all data signals that come from the MAC are ignored. Through register configuration, data can also be transmitted onto the MAC Interface. DP83867CS, DP83867IS, DP83867E SNLS504F – OCTOBER 2015 – REVISED JANUARY 2025 www.ti.com 34 Submit Document Feedback Copyright © 2025 Texas Instruments Incorporated Product Folder Links: DP83867CS DP83867IS DP83867E |
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