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DP83867CS データシート(PDF) 11 Page - Texas Instruments |
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DP83867CS データシート(HTML) 11 Page - Texas Instruments |
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11 / 129 page ![]() (4) For detailed information about DP83867 power consumption for specific supplies under a wide set of conditions, see the DP83867E/IS/CS/IR/CR RGZ Power Consumption Data application report (SNLA241). 6.6 Power-Up Timing See Figure 6-1. PARAMETER TEST CONDITIONS (1) MIN NOM MAX UNIT T1 Post power-up stabilization time prior to MDC preamble for register accesses MDIO is pulled high for 32-bit serial management initialization. 200 ms T2 Hardware configuration latch-in time from power up Hardware Configuration Pins are described in Section 7.5.1. 200 ms T3 Hardware configuration pins transition to output drivers 64 ns (1) Specified by production test, characterization, or design. 6.7 Reset Timing See Figure 6-2. PARAMETER TEST CONDITIONS (1) MIN NOM MAX UNIT T1 Post RESET stabilization time prior to MDC preamble for register accesses MDIO is pulled high for 32-bit serial management initialization. MDC can toggle during this period when MDIO remains high. 195 µs T2 Hardware configuration latch-in time from the deassertion of RESET (either soft or hard) Hardware Configuration Pins are described in Section 7.5.1. 120 ns T3 Hardware configuration pins transition to output drivers 64 ns T4 RESET pulse width X1 Clock must be stable for a minimum of 1μs during RESET pulse low time 1 µs (1) Specified by production test, characterization, or design. 6.8 MII Serial Management Timing See Figure 6-3. PARAMETER TEST CONDITIONS (1) MIN NOM MAX UNIT T1 MDC to MDIO (output) delay time 0 10 ns T2 MDIO (input) to MDC setup time 10 ns T3 MDIO (input) to MDC hold time 10 ns T4 MDC frequency 2.5 25 MHz (1) Specified by production test, characterization, or design. www.ti.com DP83867CS, DP83867IS, DP83867E SNLS504F – OCTOBER 2015 – REVISED JANUARY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 11 Product Folder Links: DP83867CS DP83867IS DP83867E |
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