DP83867CS datasheet(43/129 Pages) TI2

部品番号	DP83867CS

部品情報	DP83867E/IS/CS Robust, High Immunity, Small Form Factor 10/100/1000 Ethernet Physical Layer Transceiver

PDF	129 Pages

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メーカー	TI2 [Texas Instruments]

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10 NŸ

2.49 NŸ

VDDIO

RX_D0

5.76 NŸ

2.49 NŸ

VDDIO

RX_D2

Figure 7-13. PHY Address Strapping Example

When operating in SGMII mode, dummy straps must be added to provide a balanced load for the SGMII

differential pairs. Therefore, for SGMII applications with the straps shown in Figure 7-13, the corresponding

connections for RX_D1 and RX_D3 are shown in Figure 7-14.

10 NŸ

2.49 NŸ

VDDIO

RX_D1

5.76 NŸ

2.49 NŸ

VDDIO

RX_D3

Figure 7-14. PHY Address Strapping Example for SGMII

7.5.5 Reset Operation

The DP83867 includes an internal power-on-reset (POR) function and therefore does not need to be explicitly

reset for normal operation after power up. If required during normal operation, the device can be reset by a

hardware or software reset.

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DP83867CS, DP83867IS, DP83867E

SNLS504F – OCTOBER 2015 – REVISED JANUARY 2025

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DP83867CS データシート(PDF) 43 Page - Texas Instruments