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DP83867CS データシート(PDF) 95 Page - Texas Instruments

部品番号 DP83867CS
部品情報  DP83867E/IS/CS Robust, High Immunity, Small Form Factor 10/100/1000 Ethernet Physical Layer Transceiver
PDF  129 Pages
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メーカー  TI2 [Texas Instruments]
ホームページ  https://www.ti.com
Logo TI2 - Texas Instruments

DP83867CS データシート(HTML) 95 Page - Texas Instruments

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Table 7-114. I/O Configuration (IO_MUX_CFG), Address 0x0170 (continued)
BIT
BIT NAME
DEFAULT
DESCRIPTION
12:8
CLK_O_SEL
0 1100, RW
Clock Output Select:
01101 - 11111: RESERVED
01100: Reference clock (synchronous to XI input clock)
01011: Channel D transmit clock
01010: Channel C transmit clock
01001: Channel B transmit clock
01000: Channel A transmit clock
00111: Channel D receive clock divided by 5
00110: Channel C receive clock divided by 5
00101: Channel B receive clock divided by 5
00100: Channel A receive clock divided by 5
00011: Channel D receive clock
00010: Channel C receive clock
00001: Channel B receive clock
00000: Channel A receive clock
7
RESERVED
0, RO
RESERVED
6
CLK_O_DISABLE
0 , RW
Clock Output Disable:
1 = Disable clock output on CLK_OUT pin.
0 = Enable clock output on CLK_OUT pin.
5
RESERVED
0, RO
RESERVED
4:0
IO_IMPEDANCE_CTRL
TRIM, RW
Impedance Control for MAC I/Os:
Output impedance approximate range from 35-70Ω in 32 steps.
Lowest being 11111 and highest being 00000. Range and Step size
will vary with process.
Default is set to 50Ω by trim. But the default register value can
vary by process. Non default values of MAC I/O impedance can
be used based on trace impedance. Mismatch between device and
trace impedance can cause voltage overshoot and undershoot.
www.ti.com
DP83867CS, DP83867IS, DP83867E
SNLS504F – OCTOBER 2015 – REVISED JANUARY 2025
Copyright © 2025 Texas Instruments Incorporated
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Product Folder Links: DP83867CS DP83867IS DP83867E



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