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DP83867CS データシート(PDF) 85 Page - Texas Instruments

部品番号 DP83867CS
部品情報  DP83867E/IS/CS Robust, High Immunity, Small Form Factor 10/100/1000 Ethernet Physical Layer Transceiver
PDF  129 Pages
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メーカー  TI2 [Texas Instruments]
ホームページ  https://www.ti.com
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DP83867CS データシート(HTML) 85 Page - Texas Instruments

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7.6.51 Enable Control of Receiver's Equalizer (ECRE)
Table 7-61. Enable Control of Receiver's Equalizer (ECRE), Address 0x00C0
BIT
BIT NAME
DEFAULT
DESCRIPTION
15:0
EN_CTRL_REC_EQ
0x0000, RW
Enable control of receiver's equalizer. Value 0x0000 can further
improve the immunity margins during EMC testing.
7.6.52 PLL Clock-out Control Register (PLLCTL)
Table 7-62. PLL Clock-out Control Register (PLLCTL), Address 0x00C6
BIT
BIT NAME
DEFAULT
DESCRIPTION
15:5
RESERVED
0, RO
RESERVED: Writes ignored, read as 0.
4
CLK_MUX
0, RW
Internal Clock MUX Control:
1 = Configures analog CLK_OUT to be TX_TCLK for compliance
testing.
0 = Normal operation.
3:0
RESERVED
0, RO
RESERVED: Writes ignored, read as 0.
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DP83867CS, DP83867IS, DP83867E
SNLS504F – OCTOBER 2015 – REVISED JANUARY 2025
Copyright © 2025 Texas Instruments Incorporated
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