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EM88F758N データシート(PDF) 76 Page - ELAN Microelectronics Corp |
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EM88F758N データシート(HTML) 76 Page - ELAN Microelectronics Corp |
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76 / 190 page  EM88F758N 8-Bit Microcontroller 66 Product Specification (V1.1) 03.25.2016 (This specification is subject to change without prior notice) Bit 6 (EEDF): EEPROM detect flag 0: Write cycle is completed 1: Write cycle is unfinished Bit 5 (EEPC): EEPROM power down control bit 0: Switch of EEPROM 1: EEPROM is operating Bits 4~0: Unused bit, set to 0 all the time 6.1.100 Bank 1 R42: EERA (EEPROM Address) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 EERA7 EERA6 EERA5 EERA4 EERA3 EERA2 EERA1 EERA0 R/W R/W R/W R/W R/W R/W R/W R/W Bits 7~0 (EERA7~EERA0): EEPROM address register 6.1.101 Bank 1 R43: EERD (EEPROM Data) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 EERD7 EERD6 EERD5 EERD4 EERD3 EERD2 EERD1 EERD0 R/W R/W R/W R/W R/W R/W R/W R/W Bits 7~0 (EERD7~EERD0): EEPROM data register. 6.1.102 Bank 1 R44: FLKR (Flash Key Register for Table Write Use) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 FLK[7] FLK[6] FLK[5] FLK[4] FLK[3] FLK[2] FLK[1] FLK[0] R/W R/W R/W R/W R/W R/W R/W R/W This FLKR register is used by table write IAP mode operation. The IAP enable signal is generated when a specific value is written into this register, e.g., 0xB4. The register is designed to make sure that IAP operation occurs for flash update. 6.1.103 Bank 1 R45: TBPTL (Table Point Low Register) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TB7 TB6 TB5 TB4 TB3 TB2 TB1 TB0 R/W R/W R/W R/W R/W R/W R/W R/W Bits 7~0 (TB7~TB0): Table Point Address Bits 7~0. |
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