7733 datasheet(82/940 Pages) RENESAS

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7733 Group User's Manual

4–3

INTERRUPTS

g [S] is the initial address that the stack pointer (S) indicates when

an interrupt request is accepted.

S’s contents is “[S] – 5” after all of the above registers are pushed.

Address

[S] – 4

[S] – 3

[S] – 2

[S] – 1

[S]

Processor status register’s low-order byte (PS L)

Stack area

[S] – 5

Processor status register’s high-order byte (PS H)

Program counter’s low-order byte (PC L)

Program counter’s high-order byte (PC H)

Program bank register (PG)

When an interrupt request is accepted, the following registers’ contents immediately before acceptance of

an interrupt request are automatically pushed onto the stack area , , and in that order:

Program bank register (PG)

Program counter (PCL, PCH)

Processor status register (PSL, PSH)

Figure 4.1.2 shows the state of the stack area immediately before the program branches to an interrupt

routine.

At the end of the interrupt routine, execute the RTI instruction, which is an instruction for returning to the

routine that was executed before acceptance of an interrupt request. By executing the RTI instruction, the

above registers’ contents, which were pushed onto the stack area, are popped , , and in that order.

Then, execution of the suspended routine is resumed from where it left off.

When an interrupt request is accepted and the RTI instruction is executed, above registers ( to ) are

automatically pushed and popped. For other registers whose contents are necessary, be sure to push and

pop them by software.

4.1 Overview

Fig. 4.1.2 State of stack area immediately before program branches to interrupt routine

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