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TAS5708 データシート(PDF) 35 Page - Texas Instruments

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部品番号 TAS5708
部品情報  20-W STEREO DIGITAL AUDIO POWER AMPLIFIER WITH EQ/DRC and FEEDBACK
PDF  56 Pages
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メーカー  TI [Texas Instruments]
ホームページ  http://www.ti.com
Logo TI - Texas Instruments

TAS5708 データシート(HTML) 35 Page - Texas Instruments

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TAS5708
www.ti.com ........................................................................................................................................................................................... SLOS570 – DECEMBER 2008
4. Ramp down AVDD/DVDD while ensuring that it remains above 3V until PVCC/AVCC is below 7.5V
and observing absolute maximum ratings for digital inputs.
Table 2. Serial Control Interface Register Summary(1)
NO. OF
INITIALIZATION
SUBADDRESS
REGISTER NAME
CONTENTS
BYTES
VALUE
A u indicates unused bits.
0x00
Clock control register
1
Description shown in subsequent section
0x6C
0x01
Device ID register
1
Description shown in subsequent section
0x68
0x02
Error status register
1
Description shown in subsequent section
0x00
0x03
System control register 1
1
Description shown in subsequent section
0xA0
0x04
Serial data interface
1
Description shown in subsequent section
0x05
register
0x05
System control register 2
1
Description shown in subsequent section
0x40
0x06
Soft mute register
1
Description shown in subsequent section
0x00
0x07
Master volume
1
Description shown in subsequent section
0xFF (mute)
0x08
Channel 1 vol
1
Description shown in subsequent section
0x30 (0 dB)
0x09
Channel 2 vol
1
Description shown in subsequent section
0x30 (0 dB)
0x0A
Fine master volume
1
Description shown in subsequent section
0x00 (0 dB)
0x0B - 0X0D
1
Reserved(2)
0x0E
Volume configuration
1
Description shown in subsequent section
0x91
register
0x0F
1
Reserved(2)
0x10
Modulation limit register
1
Description shown in subsequent section
0x02
0x11
IC delay channel 1
1
Description shown in subsequent section
0x4C
0x12
IC delay channel 2
1
Description shown in subsequent section
0x34
0x13
IC delay channel 3
1
Description shown in subsequent section
0x1C
0x14
IC delay channel 4
1
Description shown in subsequent section
0x64
0x15-0x19
1
Reserved(2)
0x1A
Start/stop period register
1
Description shown in subsequent section
0x0A
0x1B
Oscillator trim register
1
Description shown in subsequent section
0x82
0x1C
BKND_ERR register
1
Description shown in subsequent section
0x02
0x1D–0x1F
1
Reserved(2)
0x20
Input MUX register
4
Description shown in subsequent section
0x 0089 777A
0x21-0x24
4
Reserved(2)
0x25
PWM MUX register
4
Description shown in subsequent section
0x0102 1345
0x26-0x28
4
Reserved(2)
0x29
ch1_bq[0]
20
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
0x2A
ch1_bq[1]
20
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
(1)
Reserved registers should not be accessed.
(2)
Reserved registers should not be accessed.
Copyright © 2008, Texas Instruments Incorporated
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