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Recommended Command Sequences

TAS5708

www.ti.com ........................................................................................................................................................................................... SLOS570 – DECEMBER 2008

PARAMETER

DESCRIPTION

MIN

TYP

MAX

UNIT

tPL-HL

Time HIZ must remain high after PDN goes low

tHL-RL

Time RESET must remain high after HIZ goes low

µs

Time digital inputs must remain valid (driven as recommended) after HIZ

tHL-DV

µs

goes low

Time digital inputs must remain valid (driven as recommended) after

tRL-DV

µs

RESET goes low

tDL-VDDH

Time digital inputs must be low before AVDD/DVDD goes below 3V

µs

tHL-PVCCH

Time PVCC/AVCC must remain above 10V after HIZ goes low

µs

tRL-PVCCH

Time PVCC/AVCC must remain above 10V after RESET goes low

µs

Time PVCC/AVCC must be below 7.5V before AVDD/DVDD goes below

tPVCCL-VDDH

µs

The DAP has two groups of commands. One set is for configuration and is intended for use only during

initialization. The other set has built-in click and pop protection and may be used during normal operation while

audio is streaming. The following supported command sequences illustrate how to initialize, operate, and

shutdown the device.

Initialization Sequence

Use the following sequence to power-up and initialize the device:

1. Hold all digital inputs low and ramp up AVDD/DVDD to at least 3V.

2. Initialize digital inputs and PVCC/AVCC supply as follows:

•

Drive RESET=0, PDN=1, HIZ=1, and other digital inputs to their desired state, observing

absolute maximum ratings relative to AVDD/DVDD. Provide stable and valid I2S clocks (MCLK,

LRCLK, and SCLK). Wait at least 100us, drive RESET=1, and wait at least another 13.5ms.

•

Ramp up PVCC/AVCC to at least 10V while ensuring it remains below 7.5V for at least 100us

after AVDD/DVDD reaches 3V. Then wait at least another 10us.

3. Trim oscillator (write 0x00 to register 0x1B) and wait at least 50ms.

4. Configure the DAP via I2C (see Users's Guide for typical values):

Biquads (0x29-36)

DRC parameters (0x3A-3C, 0x40-42, and 0x46)

Bank select (0x50)

5. Configure remaining registers

6. Exit shutdown (sequence defined below).

Normal Operation

The following are the only events supported during normal operation:

(a) Writes to master/channel volume registers

(b) Writes to soft mute register

(d) Clock errors and rate changes

Note: Events (c) and (d) are not supported for 240ms+1.3*tstart after trim following AVDD/DVDD powerup

ramp (where tstart is specified by register 0x1A).

Shutdown Sequence

Enter:

1. Ensure I2S clocks have been stable and valid for at least 50ms.

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