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TAS5708 データシート(PDF) 32 Page - Texas Instruments

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部品番号 TAS5708
部品情報  20-W STEREO DIGITAL AUDIO POWER AMPLIFIER WITH EQ/DRC and FEEDBACK
PDF  56 Pages
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メーカー  TI [Texas Instruments]
ホームページ  http://www.ti.com
Logo TI - Texas Instruments

TAS5708 データシート(HTML) 32 Page - Texas Instruments

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T0420-02
SuddenPowerLoss
(BDBTL)
AVDD/DVDD
PDN
3V
I S
2
MCLK
LRCLK
SCLK
SDIN
I C
2
SCL
SDA
t
DL-VDDH
t
PVCCL-VDDH
7.5V
10V
PVCC/AVCC
HIZ
RESET
t
PL-HL
t
HL-DV
t
HL-PVCCH
T0420-03
SuddenPowerLoss
(ADBTL)
AVDD/DVDD
PDN
3V
I S
2
MCLK
LRCLK
SCLK
SDIN
I C
2
SCL
SDA
t
DL-VDDH
t
PVCCL-VDDH
7.5V
10V
PVCC\AVCC
HIZ
RESET
t
PL-HL
t
HL-RL
t
RL-DV
t
RL-PVCCH
TAS5708
SLOS570 – DECEMBER 2008 ........................................................................................................................................................................................... www.ti.com
PARAMETER
DESCRIPTION
MIN
TYP
MAX
UNIT
tVDDH-DL
Time digital inputs must remain low after AVDD/DVDD goes above 3V
0
µs
tDL-VDDH
Time digital inputs must be low before AVDD/DVDD goes below 3V
0
µs
tVDDH-PVCCL
Time PVCC/AVCC remains below 7.5V after AVDD/DVDD goes above 3V
100
µs
Time PVCC/AVCC must be below 7.5V before AVDD/DVDD goes below
tPVCCL-VDDH
0
µs
3V
Time PVCC/AVCC must be above 10V before I2C commands may
tPVCCH-I2C
10
µs
address device
tRL-PVCCH
Time PVCC/AVCC must remain above 10V after RESET goes low
2
µs
tRH-I2C
Time RESET must be high before I2C commands may address device
13.5
ms
Time digital inputs must be valid (driven as recommended) before RESET
tDV-RH
100
µs
goes high
Time digital inputs must remain valid (driven as recommended) after
tRL-DV
2
µs
RESET goes low
Autodetect completion wait time (given stable and valid clocks) before
tautodetect
50
ms
issuing further commands
Exit shutdown wait time before issuing further commands to device (tstart
texitSD
1+1.3*tstart
ms
given by register 0x1A)
Enter shutdown wait time before issuing further commands to device (tstop
tenterSD
1+1.3*tstop
ms
given by register 0x1A)
Power-on-reset wait time after 1st trim following AVDD/DVDD power-up
tPOR
(tstart given by register 0x1A) (does not apply to trim commands following
240+1.3*tstart
ms
subsequent resets)
Figure 39. BD BTL Power Loss Sequence
Figure 40. AD BTL Power Loss Sequence
32
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Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): TAS5708



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