TAS5708 datasheet(6/56 Pages) TI

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TAS5708

SLOS570 – DECEMBER 2008 ........................................................................................................................................................................................... www.ti.com

PIN FUNCTIONS (continued)

TYPE

5-V

TERMINATION

DESCRIPTION

(1)

TOLERANT

(2)

NAME

NO.

LRCLK

5-V

Pulldown

Input serial audio data left/right clock (sample rate clock)

MCLK

5-V

Pulldown

Master Clock Input

OSC_RES

Oscillator trim resistor. Connect an 18.2-k

Ω 1% resistor to DVSSO.

OUT_A

Output, half-bridge A

OUT_B

Output, half-bridge B

OUT_C

Output, half-bridge C

OUT_D

Output, half-bridge D

PDN

5-V

Pullup

Power down, active-low. PDN prepares the device for loss of power

supplies by shutting down the Noise Shaper and initiating PWM stop

sequence.

PGND_A

5, 6

Power ground for half-bridge A

PGND_B

2, 3

Power ground for half-bridge B

PGND_C

34, 35

Power ground for half-bridge C

PGND_D

31, 32

Power ground for half-bridge D

PLL_FLTM

PLL negative loop filter terminal

PLL_FLTP

PLL positive loop filter terminal

PVCC_A

7, 8

Power supply input for half-bridge output A

PVCC_B

Power supply input for half-bridge output B

PVCC_C

Power supply input for half-bridge output C

PVCC_D

29, 30

Power supply input for half-bridge output D

RESET

5-V

Pullup

Reset, active-low. A system reset is generated by applying a logic low

to this pin. RESET is an asynchronous control signal that restores the

DAP to its default conditions, and places the PWM in the hard mute

state (tristated).

SCL

5-V

I2C serial control clock input

SCLK

5-V

Pulldown

Serial audio data clock (shift clock). SCLK is the serial audio port input

data bit clock.

SDA

DIO

5-V

I2C serial control data interface input/output

SDIN

5-V

Pulldown

Serial audio data input. SDIN supports three discrete (stereo) data

formats.

STEST

Factory test pin. Connect directly to DVSS.

FAULT

Backend error indicator. Asserted LOW for over current errors.

De-asserted upon recovery from error condition.

VR_ANA

Internally regulated 1.8-V analog supply voltage. This pin must not be

used to power external devices.

VR_DIG

Internally regulated 1.8-V digital supply voltage. This pin must not be

used to power external devices.

VCLAMP_AB

Internally generated voltage supply for channel A and B gate

drive.This pin must not be used to power external devices.Connect

only to external decoupling capacitor

VCLAMP_CD

Internally generated voltage supply for channel C and D gate

drive.This pin must not be used to power external devices.Connect

only to external decoupling capacitor

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