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TAS5708 データシート(PDF) 8 Page - Texas Instruments |
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TAS5708 データシート(HTML) 8 Page - Texas Instruments |
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8 / 56 page  PLL INPUT PARAMETERS AND EXTERNAL FILTER COMPONENTS ELECTRICAL CHARACTERISTICS TAS5708 SLOS570 – DECEMBER 2008 ........................................................................................................................................................................................... www.ti.com PARAMETER TEST CONDITIONS MIN TYP MAX UNIT fMCLKI MCLK Frequency 2.8224 24.576 MHz MCLK duty cycle 40% 50% 60% tr / Rise/fall time for MCLK 5 ns tf(MCLK) LRCLK allowable drift before LRCLK reset 4 MCLKs External PLL filter capacitor C1 SMD 0603 Y5V 47 nF External PLL filter capacitor C2 SMD 0603 Y5V 4.7 nF External PLL filter resistor R SMD 0603, metal film 470 Ω DC Characteristics, BD BTL Mode, FS = 48 kHz, TA = 25°C, PVCC_X = AVCC = 18 V, DVDD=AVDD= 3.3V, RL = 8 Ω (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VOH High-level output voltage FAULT and SDA IOH = –4 mA , 2.4 V DVDD=AVDD=3.0 V VOL Low-level output voltage FAULT and SDA IOL = 4 mA , 0.5 V DVDD=AVDD=3.0 V |VOS| Class-D output offset voltage 26 mV VBYPASS PVCC/8 reference for analog section No load 2.1 2.26 2.4 V Digital Inputs VI ≤ VIL 75 IIL Low-level input current µA DVDD = AVDD = 3.6 V Digital Inputs VI ≥ VIH 75 IIH High-level input current µA DVDD = AVDD = 3.6 V Normal mode 43 77 3.3V Supply voltage (DVDD + IDD 3.3-V supply current mA Reset (RESET = low, PDN 19 24 AVDD) = high) Normal Mode 34 60 mA ICC Half-Bridge supply current No Load (PVCC + AVCC) Reset (RESET = low, PDN 54 310 µA = high) Drain-to-source resistance, high-side VCC = 18 V , IO = 500 mA, 240 rDS(on) (1) TJ = 25°C, includes m Ω 240 Drain-to-source resistance, low-side metallization resistance Protection Undervoltage protection 8.4 Vuvp PVCC_X = AVCC falling V limit Undervoltage protection 8.5 Vuvp,hyst PVCC_X = AVCC rising V limit Over-voltage protection 27.5 Vovp PVCC_X = AVCC rising V limit Over-voltage protection 27.2 Vovp,hyst PVCC_X = AVCC falling V limit OTE(2) Over temperature error (output shutdown, unlatched) 150 °C OTEHYST (2) Extra temperature drop required to recover from error 15 °C (1) This does not include bond-wire or pin resistance. (2) Specified by design 8 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TAS5708 |
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