SN8A1702AX datasheet(37/112 Pages) SONIX

37 / 112 page

Preliminary

SN8P1702A/SN8P1703A

8-bit micro-controller build-in 12-bit ADC

SONiX TECHNOLOGY CO., LTD

Page 37

Revision 0.5

5 SYSTEM REGISTER

OVERVIEW

The system special register is located at 80h~FFh. The main purpose of system registers is to control the peripheral

hardware of the chip. Using system registers can control I/O ports, SIO, ADC, PWM, timers and counters by

programming. The Memory map provides an easy and quick reference source for writing application program. To

accessing these system registers is controlled by the select memory bank (RBANK = 0) or the bank 0 read/write

instruction (B0MOV, B0BSET, B0BCLR…).

SYSTEM REGISTER ARRANGEMENT (BANK 0)

BYTES of SYSTEM REGISTER

SN8P1702

PFLAG

P4CON

ADM

ADB

ADR

PEDGE

P1W

P1M

P4M

P5M

INTRQ

INTEN

OSCM

TC0R

PCL

PCH

T0M

TC0M

TC0C

TC1M

TC0C

TC1R

STKP

E P0UR

P1UR

P4UR

P5UR

@YZ

STK7

STK6

STK5

STK4

STK3

STK2

STK1

STK0

Table 5-1. System Register Arrangement

Description

PFLAG = ROM page and special flag register.

R = Working register and ROM lookup data buffer.

ADB = ADC’s data buffer.

Y, Z = Working, @YZ and ROM addressing register.

PnM = Port n input/output mode register.

RBANK = RAM Bank Select register.

INTRQ = Interrupts’ request register.

ADM = ADC’s mode register.

OSCM = Oscillator mode register.

ADR = ADC’s resolution selects register.

TC0/1M = Timer/Counter 0/1 mode register.

P1W = Port 1 wakeup register.

TC0/1C = Timer/Counter 0/1 counting register.

Pn = Port n data buffer.

TC0/1R = Timer/Counter 0/1 auto-reload data buffer.

PnUR= Pull-up register

STKP = Stack pointer buffer.

INTEN = Interrupts’ enable register.

@HL = RAM HL indirect addressing index pointer.

PCH, PCL = Program counter.

STK0~STK7 = Stack 0 ~ stack 7 buffer.

@YZ = RAM YZ indirect addressing index pointer.

Note:

a). All of register names had been declared in SONiX 8-bit MCU assembler.

b). One-bit name had been declared in SONiX 8-bit MCU assembler with “F” prefix code.

c). It will get logic “H” data, when use instruction to check empty location.

d). The low nibble of ADR register is read only.

e). “b0bset”, “b0bclr”, ”bset”, ”bclr” instructions only support “R/W” registers.

SN8A1702AX データシート(PDF) 37 Page - SONiX Technology Company

SN8A1702AX データシート(HTML) 37 Page - SONiX Technology Company

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

データシートダウンロード