SN8A1702AX datasheet(53/112 Pages) SONIX

53 / 112 page

Preliminary

SN8P1702A/SN8P1703A

8-bit micro-controller build-in 12-bit ADC

SONiX TECHNOLOGY CO., LTD

Page 53

Revision 0.5

8 TIMERS COUNTERS

WATCHDOG TIMER (WDT)

The watchdog timer (WDT) is a binary up counter designed for monitoring program execution. If the program gets in

the unknown status by noise interference, The WDT’s overflow signal will reset this chip and restart operation. The

instruction that clear the watch-dog timer (B0BSET

FWDRST) should be executed at proper points in a program

within a given period. If an instruction that clears the watchdog timer is not executed within the period and the

watchdog timer overflows, reset signal is generated and system is restarted with reset status. In order to generate

different output timings, the user can control watchdog timer by modifying the Wdrate control bits of OSCM register.

The watchdog timer will be disabled at green and power down modes.

OSCM initial value = 0000 000x

0CAH

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

OSCM

WTCKS

WDRST

Wdrate

CPUM1

CPUM0

CLKMD

STPHX

R/W

Bit1

STPHX: External high-speed oscillator control bit.

0 = free run,

1 = stop.

Note: This bit only controls external high-speed oscillator. If STPHX=1, the internal low-speed RC

oscillator is still running.

Bit2

CLKMD: System high/Low speed mode select bit.

0 = normal (dual) mode,

1 = slow mode.

Bit[4:3] CPUM[1:0]: CPU operating mode control bit.

00 = normal,

01 = sleep (power down) mode,

10 = green mode,

11 = reserved.

Bit5

Wdrate: Watchdog timer rate select bit.

0 = Fcpu

÷ 214

1 = Fcpu

÷ 28

Bit6

WDRST: Watchdog timer reset bit.

0 = Non reset,

1 = clear the watchdog timer’s counter.

(The detail information is in watchdog timer chapter.)

Bit7

WTCKS: Watchdog clock source select bit.

0 = Fcpu,

1 = internal RC low clock.

WTCKS

WTRATE

CLKMD

Watchdog Timer Overflow Time

1 / ( Fcpu

÷ 214 ÷ 16 ) = 293 ms, Fosc=3.58MHz

1 / ( Fcpu

÷ 28 ÷ 16 ) = 500 ms, Fosc=32768Hz

1 / ( Fcpu

÷ 214 ÷ 16 ) = 65.5s, Fosc=16KHz@3V

1 / ( Fcpu

÷ 28 ÷ 16 ) = 1s, Fosc=16KHz@3V

1 / ( 16K

÷ 512 ÷ 16 ) ~ 0.5s @3V

Table 8-1. Watchdog timer overflow timetable

SN8A1702AX データシート(PDF) 53 Page - SONiX Technology Company

SN8A1702AX データシート(HTML) 53 Page - SONiX Technology Company

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

データシートダウンロード

リンク URL

SN8A1702AX データシート(PDF) 53 Page - SONiX Technology Company

SN8A1702AX データシート(HTML) 53 Page - SONiX Technology Company

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

データシート ダウンロード

リンク URL

データシートダウンロード