MRF49XA-ISLASHT datasheet(41/102 Pages) MICROCHIP

41 / 102 page

Preliminary

DS70590C-page 41

MRF49XA

PLLCREG: PLL CONFIGURATION REGISTER (POR: 0xCC77)

W-1

W-0

W-1

W-0

CCB<15:8>

bit 15

bit 8

W-0

W-1

W-0

W-1

—

CBTC<1:0>

PDDS

PLLDD

PLLBWB

bit 7

bit 0

Legend:

r = reserved bit

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 15-8

CCB<15:8>: Command Code bits

The command code bits (11001100b) are serially sent to the microcontroller to identify the bits to be

written in the PLLCREG.

bit 7

Unimplemented: Write as ‘0’

bit 6-5

CBTC<1:0>: Clock Buffer Time Control bits

These bits control the rise and fall time for the clock buffer which is dependant on the output clock

frequency from the BCSREG.

11 = 5 MHz - 10 MHz

10 = 3.3 MHz

01 = 2.5 MHz or less

00 = 2.5 MHz or less

bit 4

Reserved: Masked to ‘1’

bit 3

PDDS: Phase Detector Delay Switch bit

1 = Enables the phase detector delay function

0 = Disables the phase detector delay function

bit 2

PLLDD: PLL Dithering Disable bit

1 = Disables PLL dithering

0 = Enables PLL dithering

bit 1

Reserved: Write as ‘1’

bit 0

PLLBWB: PLL Bandwidth bit

Enabling the bit configures higher data rates, faster settling and reduced phase noise; thus, resulting

in a better RF performance.

1 = -102 dBc/Hz, > 90 kbps (max 256 kbps)

0 = -107 dBc/Hz, < 90 kbps (max 86.2 kbps)

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