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MRF49XA-I/T データシート(PDF) 93 Page - Microchip Technology |
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MRF49XA-I/T データシート(HTML) 93 Page - Microchip Technology |
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93 / 102 page  © 2009-2011 Microchip Technology Inc. Preliminary DS70590C-page 93 MRF49XA APPENDIX A: READ SEQUENCE AND PACKET STRUCTURES Figure 1 shows the STSREG read sequence with FIFO read as an example. FIGURE A-1: STSREG READ SEQUENCE Note: 1. Applicable when the RXCEN bit is set using the PMCREG. 2. Applicable when the RXCEN bit is cleared using the PMCREG. 3. These bits are internally latched and the other bits are only multiplexed out. SCK 0 1 3 4 2 5 6 7 8 9 10 11 12 13 14 15 16 17 POR TXRXFIFO CLKRL TXOWR XOF WUTI NT LCE XINT LBTD FIFO EM ATRS SI DQDO OFFSV AFCCT (Latched) OFFSB <3> OFFSB <2> OFFSB <1> OFFSB <0> FO FO+1 FO+2 (Latched) (Latched) (Latched) (Latched) (Sign) Command FIFO Out Status Bits Out Interrupt Bits Out SDI SDO CS (1)(2)(3) (1,2,3) (1,2,3) TABLE A-1: RECOMMENDED FIFO PACKET STRUCTURES Length Preamble Synchronous Word/Network ID Payload CRC Minimum Length 4-8 bits (0x0A or 0x05) 0xD4 (programmable) — 4-bit-1 byte Recommended Length 8-12 bits (e.g., 0xAA or 0x55) 0x2DD4 (D4 is programmable) — 2 bytes |
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