MRF49XA-ISLASHT datasheet(18/102 Pages) MICROCHIP

18 / 102 page

MRF49XA

DS70590C-page 18

Preliminary

2.16

Memory Organization

The memory in MRF49XA is implemented as static

RAM and is accessible through the SPI port. Each

memory location functionally addresses a register, con-

trol, status or data/FIFO fields, as shown in Table 2-10.

The command/control registers provide control, status

and device address for transceiver operations. The

FIFOs serve as temporary buffers for data transmission

and reception.

The commands to the device are sent serially. All

17 commands basically address the 17 registers

affiliated to it. The registers consist of a command

code, followed by control, data, status or parameter

bits. The MSb is sent first in all of the commands (e.g.,

bit 15 for a 16-bit command). The POR circuit sets the

default values in all control and command registers.

In general, MRF49XA registers are read only. Hence

the chip status can only be read by the Status Read

to the desired register. It is not desired to read/write all

registers and there is no way to read back the register.

TABLE 2-4:

CONTROL (COMMAND) REGISTER DESCRIPTION

SI. No. Register Name

Related Control Functions

STSREG

Status Read Register

Receive register/FIFO, transmit register,

interrupt, frequency control and signal

strength, POR, wake-up timer, low battery

detect, data quality, clock recovery

GENCREG

General Configuration Register

Frequency band select, enables TX and RX

registers, crystal load capacitor bank value

AFCCREG

AFC Configuration Register

AFC locking range, mode, accuracy and

enable

TXCREG

Transmit Configuration Register

Modulation polarity, modulation bandwidth,

transmit power and deviation

TXBREG

Transmit Byte Register

Transmit data byte

CFSREG

Center Frequency Value Set Register

Transmit or receive frequency

RXCREG

Receive Control Register

Function of pin 16, DIO mode, RX BBBW,

LNA gain, digital RSSI threshold

BBFCREG

Baseband Filter Configuration Register

Clock Recovery mode, data indicator

parameter value and filter type

RXFIFOREG

Receiver FIFO Read Register

Receive data byte

FIFORSTREG FIFO and Reset mode Configuration

FIFO interrupt level, FIFO start control and

FIFO enable, POR Sensitivity mode,

synchronous character length

SYNBREG

Synchronous Byte Configuration Register

Synchronous character pattern

DRSREG

Data Rate Value Set Register

Data rate prescalar set

PMCREG

Power Management Configuration Register Enables receive and transmit chain,

baseband circuit, synthesizer circuit,

oscillator, wake-up timer, low battery detect

and clock out

WTSREG

Wake-up Timer Value Set Register

Wake-up timer values for time interval

DCSREG

Duty Cycle Value Set Register

Duty Cycle mode and value

BCSREG

Battery Threshold Detect and Clock Output

Value Set Register

Low battery detect threshold values and

clock output frequency

PLLCREG

PLL Configuration Register

Clock out buffer speed, PLL bandwidth,

dithering and delay

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