MRF49XA-ISLASHT datasheet(68/102 Pages) MICROCHIP

68 / 102 page

MRF49XA

DS70590C-page 68

Preliminary

The device transmit sequence should be performed as

follows:

Enable the TX register by setting TXDEN = 1.

The TX register is automatically filled with

0xAAAA, which can be used to generate

preamble.

Enable the transmitter by setting TXCEN = 1.

The synthesizer and the PLL turns on, calibrates

itself and the PA is automatically enabled.

The TX data transmission starts.

On completion of byte transmission, the IRO pin

goes high and the SDO pin goes low

simultaneously. The IRO pulse shows that the

first 8 bits (the first byte by default, 0xAA) have

been transmitted. There are still 8 bits in the

transmit register.

The microcontroller recognizes the interrupt and

writes a data byte to the TXBREG.

Repeat steps 6 and 7 until the last data byte is

reached.

Using the same method, transmit a dummy byte.

The value of this dummy byte can be anything.

10. The next high-to-low transition on the IRO line

(or low-to-high on the SDO pin) shows that the

transmission of the data bytes has ended. The

dummy byte is still in the TX latch.

11. Turn off the transmitter by setting the bit,

TXCEN = 0. This event probably happens while

the dummy byte is being transmitted. Since the

dummy byte contains no useful information, this

corruption will not cause any problem.

12. Clearing the TXDEN bit clears the register

underrun interrupt. The IRO pin goes high and

the SDO pin goes low.

The transmit sequence is illustrated in Figure 3-16. For

details on transmit pin function configuration, see

Table 3-3. The TXDEN bit is in the GENCREG register

and enables the Transmit Data register.

The transmit sequence can be performed without

sending a dummy byte (step 1), but after loading the

last data byte to the transmit register, the PA turn off

should be delayed for at least 16 bits time. The

microcontroller clock source (if the clock is not supplied

by the transceiver) should be stable enough over

temperature and voltage ranges to ensure this

minimum delay under all operating circumstances.

When the dummy byte is used, the whole process is

driven by interrupts. Changing the TX data rate has no

effect on the algorithm and no accurate delay

measurement is needed. Figure 3-17 shows the

multi-byte transmit write sequence.

The registers associated with transmission are:

•STSREG (see Register 2-1)

• GENCREG (see Register 2-2)

• TXCREG (see Register 2-4)

• TXBREG (see Register 2-5)

• PMCREG (see Register 2-13)

TABLE 3-3:

TRANSMIT PIN FUNCTION VS. OPERATION MODE

Mode

Bit Setting

Function

Pin 6

Pin 7

Transmit

TXDEN = 0

Internal TX Data register disabled

TX data input

Not used

TXDEN = 1

Internal TX Data register enabled

FSEL input

(TX Data register can be

accessed)

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