LT1956IGN datasheet(18/28 Pages) LINER

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LT1956/LT1956-5

1956f

Board layout also has a significant effect on thermal resis-

tance. For the GN package, Pins 1, 8, 9 and 16, GND, are

a continuous copper plate that runs under the LT1956 die.

This is the best thermal path for heat out of the package.

Reducing the thermal resistance from Pins 1, 8, 9 and 16

onto the board will reduce die temperature and increase

the power capability of the LT1956. This is achieved by

providing as much copper area as possible around these

pins. Adding multiple solder filled feedthroughs under and

around these four corner pins to the ground plane will also

help. Similar treatment to the catch diode and coil termi-

nations will reduce any additional heating effects. For the

FE package, the exposed pad should be soldered to the

copper ground plane underneath the device.

PARASITIC RESONANCE

Resonance or “ringing” may sometimes be seen on the

switch node (see Figure 7). Very high frequency ringing

following switch rise time is caused by switch/diode/input

capacitor lead inductance and diode capacitance. Schot-

tky diodes have very high “Q” junction capacitance that

can ring for many cycles when excited at high frequency.

If total lead length for the input capacitor, diode and switch

path is 1 inch, the inductance will be approximately 25nH.

At switch off, this will produce a spike across the NPN

output device in addition to the input voltage. At higher

currents this spike can be in the order of 10V to 20V or

higher with a poor layout, potentially exceeding the abso-

lute max switch voltage. The path around switch, catch

diode and input capacitor must be kept as short as

possible to ensure reliable operation. When looking at this,

APPLICATIO S I FOR ATIO

a >100MHz oscilloscope must be used, and waveforms

should be observed on the leads of the package. This

switch off spike will also cause the SW node to go below

ground. The LT1956 has special circuitry inside which

mitigates this problem, but negative voltages over 0.8V

lasting longer than 10ns should be avoided. Note that

100MHz oscilloscopes are barely fast enough to see the

details of the falling edge overshoot in Figure 7.

A second, much lower frequency ringing is seen during

switch off time if load current is low enough to allow the

inductor current to fall to zero during part of the switch off

time (see Figure 8). Switch and diode capacitance resonate

with the inductor to form damped ringing at 1MHz to 10

MHz. This ringing is not harmful to the regulator and it has

not been shown to contribute significantly to EMI. Any

attempt to damp it with a resistive snubber will degrade

efficiency.

THERMAL CALCULATIONS

Power dissipation in the LT1956 chip comes from four

sources: switch DC loss, switch AC loss, boost circuit

current, and input quiescent current. The following formu-

las show how to calculate each of these losses. These

formulas assume continuous mode operation, so they

should not be used for calculating efficiency at light load

currents.

Switch loss:

SW OUT

OUT

EFF

OUT

() (

)

()( )( )

(/ )

Figure 7. Switch Node Resonance

50ns/DIV

1956 F07

2V/DIV

SW RISE

SW FALL

SWITCH NODE

VOLTAGE

INDUCTOR

CURRENT AT

IOUT = 0.1A

VIN = 25V

500ns/DIV

1956 F08

VOUT = 5V

L = 15

µH

Figure 8. Discontinuous Mode Ringing

10V/DIV

0.2A/DIV

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