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LT1956IGN データシート(PDF) 23 Page - Linear Technology |
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LT1956IGN データシート(HTML) 23 Page - Linear Technology |
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23 / 28 page ![]() 23 LT1956/LT1956-5 1956f APPLICATIO S I FOR ATIO current via the VC pin to maintain a constant dv/dt at the output. Output rise time is controlled by the current through CSS defined by R4 and Q1’s VBE. Once the output is in regulation, Q1 turns off and the circuit operates normally. R3 is transient protection for the base of Q1. Rise Time RC V V SS OUT BE = ()( )( ) 4 Using the values shown in Figure 10, Rise Time ms = ()( )() = 47 10 15 10 5 07 5 39 •• . – The ramp is linear and rise times in the order of 100ms are possible. Since the circuit is voltage controlled, the ramp rate is unaffected by load characteristics and maximum output current is unchanged. Variants of this circuit can be used for sequencing multiple regulator outputs. DUAL POLARITY OUTPUT CONVERTER The circuit in Figure 14a generates both positive and negative 5V outputs with all components under 3mm height. The topology for the 5V output is a standard buck converter. The –5V output uses a second inductor L2, diode D3 and output capacitor C6. The capacitor C4 5V, 1A REMOVABLE INPUT C2 0.1 µF CF 220pF RC 2.2k R3 54k D1 10MQ060N 1956 F12 C3 2.2 µF D3 10MQ060N MMSD914TI L1 18 µH CC 0.022 µF C1 100 µF 10V ALTERNATE SUPPLY R4 25k R1 15.4k R2 4.99k BOOST VIN LT1956 SHDN SYNC SW BIAS FB VC GND + Figure 12. Dual Source Supply with 25 µA Reverse Leakage OUTPUT 5V 1A INPUT 12V 1766 F13 C2 0.1 µF C1 100 µF CSS 15nF D1 C3 2.2 µF CERAMIC D2 MMSD914TI L1 18 µH R1 15.4k R3 2k R2 4.99k R4 47k Q1 RC 2.2k CF 220pF CC 0.022 µF BOOST BIAS VIN LT1956 SHDN SYNC SW FB VC GND + Figure 13. Buck Converter with Adjustable Soft-Start |
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