TAS5731MPHPR datasheet(26/68 Pages) TI1

26 / 68 page

TAS5731M

SLOS838B – JULY 2013 – REVISED NOVEMBER 2013

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DEVICE PROTECTION SYSTEM

Overcurrent (OC) Protection With Current Limiting

The device has independent, fast-reacting current detectors on all high-side and low-side power-stage FETs. The

detector outputs are closely monitored by a protection system. If the high-current condition situation persists, i.e.,

the power stage is being overloaded, a protection system triggers a latching shutdown, resulting in the power

stage being set in the high-impedance (Hi-Z) state. The device returns to normal operation once the fault

condition (i.e., a short circuit on the output) is removed. Current-limiting and overcurrent protection are not

independent for half-bridges. That is, if the bridge-tied load between half-bridges A and B causes an overcurrent

fault, half-bridges A, B, C, and D are shut down.

Overtemperature Protection

The TAS5731M has an overtemperature-protection system. If the device junction temperature exceeds 150°C

(nominal), the device is put into thermal shutdown, resulting in all half-bridge outputs being set in the high-

impedance (Hi-Z) state. The TAS5731M recovers automatically once the temperature drops approximately 30°C.

Undervoltage Protection (UVP) and Power-On Reset (POR)

The UVP and POR circuits of the TAS5731M fully protect the device in any power-up/down and brownout

situation. While powering up, the POR circuit resets the overload circuit (OLP) and ensures that all circuits are

fully operational when the PVDD and AVDD supply voltages reach 7.6 V and 2.7 V, respectively. Although PVDD

and AVDD are independently monitored, a supply-voltage drop below the UVP threshold on AVDD or either

PVDD pin results in all half-bridge outputs immediately being set in the high-impedance (Hi-Z) state.

SSTIMER FUNCTIONALITY

The SSTIMER pin uses a capacitor connected between this pin and ground to control the output duty cycle when

exiting all-channel shutdown. The capacitor on the SSTIMER pin is slowly charged through an internal current

source, and the charge time determines the rate at which the output transitions from a near-zero duty cycle to the

desired duty cycle. This allows for a smooth transition that minimizes audible pops and clicks. When the part is

shut down, the drivers are placed in the high-impedance state and transition slowly down through a 3-k

Ω resistor,

similarly minimizing pops and clicks. The shutdown transition time is independent of the SSTIMER pin

capacitance. Larger capacitors increase the start-up time, while capacitors smaller than 2.2 nF decrease the

start-up time. The SSTIMER pin should be left floating for BD modulation.

CLOCK, AUTODETECTION, AND PLL

The TAS5731M is an I2S slave device. It accepts MCLK, SCLK, and LRCLK. The digital audio processor (DAP)

supports all the sample rates and MCLK rates that are defined in the clock control register .

The TAS5731M checks to verify that SCLK is a specific value of 32 fS, 48 fS, or 64 fS. The DAP only supports a 1

× fS LRCLK. The timing relationship of these clocks to SDIN is shown in subsequent sections. The clock section

uses MCLK or the internal oscillator clock (when MCLK is unstable, out of range, or absent) to produce the

internal clock (DCLK) running at 512 times the PWM switching frequency.

The DAP can autodetect and set the internal clock control logic to the appropriate settings for all supported clock

rates as defined in the clock-control register.

The TAS5731M has robust clock error handling that uses the built-in trimmed oscillator clock to quickly detect

changes/errors. Once the system detects a clock change/error, it mutes the audio (through a single-step mute)

and then forces PLL to limp using the internal oscillator as a reference clock. Once the clocks are stable, the

system autodetects the new rate and reverts to normal operation. During this process, the default volume is

restored in a single step (also called hard unmute). The ramp process can be programmed to ramp back slowly

(also called soft unmute) as defined in volume register (0x0E).

SERIAL DATA INTERFACE

Serial data is input on SDIN. The PWM outputs are derived from SDIN. The TAS5731M DAP accepts serial data

in 16-, 20-, or 24-bit left-justified, right-justified, and I2S serial data formats.

Product Folder Links :TAS5731M

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