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TAS5731MPHPR データシート(PDF) 54 Page - Texas Instruments

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部品番号 TAS5731MPHPR
部品情報  2 * 30-W DIGITAL AUDIO POWER AMPLIFIER WITH DSP AND 2.1 MODE
PDF  68 Pages
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メーカー  TI1 [Texas Instruments]
ホームページ  http://www.ti.com
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TAS5731MPHPR データシート(HTML) 54 Page - Texas Instruments

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TAS5731M
SLOS838B – JULY 2013 – REVISED NOVEMBER 2013
www.ti.com
OSCILLATOR TRIM REGISTER (0x1B)
The TAS5731M PWM processor contains an internal oscillator to support autodetect of I2S clock rates. This
reduces system cost because an external reference is not required. Currently, TI recommends a reference
resistor value of 18.2 k
Ω (1%). This should be connected between OSC_RES and DVSSO.
Writing 0x00 to register 0x1B enables the trim that was programmed at the factory.
Note that trim must always be run following reset of the device.
Table 17. Oscillator Trim Register (0x1B)
D7
D6
D5
D4
D3
D2
D1
D0
FUNCTION
0
–
–
–
–
–
–
–
Reserved (1)
–
0
–
–
–
–
–
–
Oscillator trim not done (read-only) (1)
–
1
–
–
–
–
–
–
Oscillator trim done (read only)
–
–
0
0
0
0
–
–
Reserved (1)
–
–
–
–
–
–
0
–
Select factory trim (Write a 0 to select factory trim; default is 1.)
–
–
–
–
–
–
1
–
Factory trim disabled (1)
–
–
–
–
–
–
–
0
Reserved (1)
(1)
Default values are in bold.
BKND_ERR REGISTER (0x1C)
When a back-end error signal is received from the internal power stage, the power stage is reset stopping all
PWM activity. Subsequently, the modulator waits approximately for the time listed in Table 18 before attempting
to re-start the power stage.
Table 18. BKND_ERR Register (0x1C)(1)
D7
D6
D5
D4
D3
D2
D1
D0
FUNCTION
0
0
0
0
0
0
0
X
Reserved
–
–
–
–
0
0
1
0
Set back-end reset period to 299 ms (2)
–
–
–
–
0
0
1
1
Set back-end reset period to 449 ms
–
–
–
–
0
1
0
0
Set back-end reset period to 598 ms
–
–
–
–
0
1
0
1
Set back-end reset period to 748 ms
–
–
–
–
0
1
1
0
Set back-end reset period to 898 ms
–
–
–
–
0
1
1
1
Set back-end reset period to 1047 ms
–
–
–
–
1
0
0
0
Set back-end reset period to 1197 ms
–
–
–
–
1
0
0
1
Set back-end reset period to 1346 ms
–
–
–
–
1
0
1
X
Set back-end reset period to 1496 ms
–
–
–
–
1
1
X
X
Set back-end reset period to 1496 ms
(1)
This register can be written only with a "non-Reserved" value. Also this register can be written once after the reset.
(2)
Default values are in bold.
54
Copyright © 2013, Texas Instruments Incorporated
Product Folder Links :TAS5731M



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