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TAS5731MPHPR データシート(PDF) 30 Page - Texas Instruments

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部品番号 TAS5731MPHPR
部品情報  2 * 30-W DIGITAL AUDIO POWER AMPLIFIER WITH DSP AND 2.1 MODE
PDF  68 Pages
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メーカー  TI1 [Texas Instruments]
ホームページ  http://www.ti.com
Logo TI1 - Texas Instruments

TAS5731MPHPR データシート(HTML) 30 Page - Texas Instruments

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23
22
SCLK
32Clks
LRCLK
LeftChannel
24-BitMode
1
20-BitMode
16-BitMode
15
14
MSB
LSB
SCLK
32Clks
RightChannel
2-ChannelRight-Justified(SonyFormat)StereoInput
T0034-03
19
18
1
19
18
1
0
0
0
15
14
15
14
23
22
1
15
14
MSB
LSB
19
18
1
19
18
1
0
0
0
15
14
15
14
SCLK
16Clks
LRCLK
LeftChannel
16-BitMode
1
1
15
15
14
14
MSB
LSB
16Clks
RightChannel
2-ChannelLeft-JustifiedStereoInput
T0266-02
3
3
2
2
5
5
4
4
9
9
8
8
0
0
13
13
10
10
11
11
12
12
SCLK
MSB
LSB
TAS5731M
SLOS838B – JULY 2013 – REVISED NOVEMBER 2013
www.ti.com
NOTE: All data presented in 2s-complement form with MSB first.
Figure 51. Left-Justified 32-fS Format
Right-Justified
Right-justified (RJ) timing uses LRCLK to define when the data being transmitted is for the left channel and when
it is for the right channel. LRCLK is high for the left channel and low for the right channel. A bit clock running at
32, 48, or 64 × fS is used to clock in the data. The first bit of data appears on the data 8 bit-clock periods (for 24-
bit data) after LRCLK toggles. In RJ mode, the LSB of data is always clocked by the last bit clock before LRCLK
transitions. The data is written MSB-first and is valid on the rising edge of bit clock. The DAP masks unused
leading data bit positions.
Figure 52. Right-Justified 64-fS Format
30
Copyright © 2013, Texas Instruments Incorporated
Product Folder Links :TAS5731M



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