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106

Revision 3.1

Integrated Functions (Continued)

4.3.3

SDRAM Commands

This subsection discusses the SDRAM commands sup-

ported by the memory controller. Table 4-13 summarizes

these commands followed by detailed operational infor-

mation regarding each command.

MRS — The Mode Register command defines the specific

mode of operation of the SDRAM. This definition includes

the selection of burst length, burst type, and CAS latency.

CAS latency is the delay, in clock cycles, between the reg-

istration of a read command and the availability of the first

piece of output data.

The burst length is programmed by address bits MA[2:0],

the burst type by address bit MA3 and the CAS latency by

address bits MA[6:4].

The memory controller only supports a burst length of two

and burst type of interleave.

The field value on MA[12:0] and BA[1:0] during the MRS

cycleare as shownin Table4-14.

PRE — The precharge command is used to deactivate

the open row in a particular bank or the open row in both

component banks. Address pin MA10 determines whether

one or both banks are to be precharged. In the case

where only one component bank is to be precharged,

BA[1:0] selects which bank. Once a bank has been pre-

charged, it is in the Idle state and must be activated prior

to any read or write commands.

Table 4-13. Basic Command Truth Table

Name

Command

RAS

CAS

MRS

Mode Register Set

PRE

Bank Precharge

ACT

Bank activate/row-

address entry

WRT

Column address

entry/Write operation

LHL

READ

Column address

entry/Read operation

LHL

DESL

Control input inhibit/

No operation

XXX

REFR*

CBR Refresh or Auto

Refresh

Note: *This command is CBR (CAS-before-RAS) refresh

when CKE is high and self refresh when CKE is low.

Table 4-14. Address Line Programming during MRS Cycles

BA[1:0]

MA[12:7]

MA[6:4]

MA3

MA2

MA1

MA0

000000

CAS Latency:

000 = Reserved

010 = 2 CLK

100 = 4 CLK

110 = 6 CLK

001 = 1 CLK

011 = 3 CLK

101 = 5 CLK

111 = 7 CLK

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