GXM datasheet(109/244 Pages) NSC

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Integrated Functions (Continued)

25:23

MEMHDCTL

Control High Drive/Slew Control: Controls the high drive and slew rate of the memory control sig-

nals (CASA#, CASB#, RASA#, RASB#, CKEA, CKEB, WEA#, WEA#, DQM[7:0], and CS[3:0]#):

000 = Tristate

001 = Smallest drive strength

010 -110 = Represents gradual drive strength increase

111 = Highest drive strength

RSVD

Reserved: Set to 0.

RSVD

Reserved: Must be set to 0. Wait state on the X-Bus x_data during read cycles - for debug only.

20:18

SDCLKRATE

SDRAM Clock Ratio: Selects SDRAM clock ratio:

000 = Reserved

100 = ÷ 3.5

001 = ÷ 2

101 = ÷ 4

010 = ÷ 2.5

110 = ÷ 4.5

011 = ÷ 3 (Default)

111 = ÷ 5

Ratio does not take effect until the SDCLKSTRT bit (bit 17 of this register) transitions from 0 to 1.

SDCLKSTRT

Start SDCLK: Start operating SDCLK using the new ratio and shift value (selected in bits [20:18] of

this register): 0 = Clear; 1 = Enable.

This bit should be cleared every time before a one is written to it in order to start SDCLK or to change

the shift value.

16:8

RFSHRATE

Refresh Interval: This field determines the number of processor core clocks multiplied by 64 between

refresh cycles to the DRAM. By default, the refresh interval is 00h. This implies that refresh is turned

off by default.

7:6

RFSHSTAG

Refresh Staggering: This field determines number of clocks between REF commands to different

banks during refresh cycles:

00 = 0 SDRAM clocks

10 = 2 SDRAM clocks

01 = 1 SDRAM clocks (Default)

11 = 4 SDRAM clocks

Staggering is used to help reduce power spikes during refresh. When only DIMM0 is installed and it

has only one DIMM bank, then this field must be set to 00.

2CLKADDR

Two Clock Address Setup: Assert memory address for one extra clock before CS# is asserted:

0 = Disable; 1 = Enable.

This can be used to compensate for address setup at high frequencies.

4RFSHTST

Test Refresh: This bit, when set high, generates a refresh request. This bit is only used for testing

purposes.

XBUSARB

X-Bus Round Robin: When enabled, processor requests are arbitrated at the same priority level than

graphics pipeline requests and non-critical display controller requests. When disabled, processor

requests are arbitrated at a higher priority level. High priority display controller requests always have

the highest arbitration priority: 0 = Enable; 1 = Disable.

2VGAWRP

VGA Wrap Enable: Allow memory wrapping into the VGA memory address space from A0000h to

BFFFFh: 0 = Disable; 1 = Enable.

1RSVD

Reserved: Set to 0.

SDRAMPRG

Program SDRAM: When this bit is set the memory controller will program the SDRAM MRS register

using LTMODE in MC_SYNC_TIM1.

This bit should be cleared every time before a one is written to it in order to program the SDRAM.

GX_BASE+8404h-8407h

MC_MEM_CNTRL2 (R/W)

Default Value = 00000801h

31:18

RSVD

Reserved: Set to 0.

17:16

SDCLKRISE

SDCLK Rising Delay: Controls the delay between the core clock and the rising edge of SDCLK dur-

ing all modes. (Set by BIOS.)

15:14

SDCLKFALL

SDCLK Falling Delay: Controls the delay between the core clock and the falling edge of SDCLK dur-

ing 2.5 and 3.5 clock modes. (Set by BIOS.)

13:11

SDCLKHDCTL

SDCLK High Drive/Slew Control: Controls the high drive and slew rate of SDCLK[3:0] and

SDCLK_OUT.

000 = Highest drive strength. (No braking applied in the pads)

001 = Smallest drive strength

010 -110 = Represent gradual drive strength increase

111 = Highest drive strength

SDCLKOMSK

Mask SDCLK_OUT: 0 = Not masked; 1 = Mask.

Table 4-16. Memory Controller Registers (Continued)

Bit

Name

Description

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