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L6759D データシート(PDF) 17 Page - STMicroelectronics |
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L6759D データシート(HTML) 17 Page - STMicroelectronics |
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17 / 51 page  L6759D Device configuration and pin-strapping tables Doc ID 023240 Rev 1 17/51 4 Device configuration and pin-strapping tables The L6759D is fully compliant with Intel® VR12/IMVP7 SVID protocol Rev1.5, document # 456098. To guarantee proper device and CPU operations, refer to this document for bus design and layout guidelines. Different platforms may require different pull-up impedance on the SVI bus. Impedance matching and spacing between SVDATA, SVCLK, and ALERT# must be followed. 4.1 JMode When enabled, single-phase is an independent regulator with 0.75 V fixed reference (load- line disabled - TM can be used as enable for the single-phase). Output voltage higher than the internal reference may be achieved by adding a proper resistor divider (RA, RB - see Figure 5). To maintain precision in output voltage regulation, it is recommended to provide both SFBR and SRGND with the same divider. Equation 1 Figure 5. JMode: voltage positioning V OUT 0.750V RA RB + RB ----------------------- ⋅ = 0.750V SFB SCOMP SVSEN SFBR RF CF RFB To Vout (Remote Sense) SRGND RA RA RB RB |
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