SLG46110V datasheet(64/82 Pages) DIALOG

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SLG46110

15.2 POR Sequence

The POR system generates a sequence of signals that enable certain macrocells. The sequence is shown in Figure 43.

As can be seen from Figure 43 after the VDD has start ramping up and crosses the Power_ON threshold, first, the on-chip NVM

memory is reset. Next the chip reads the data from NVM, and transfers this information to SRAM registers that serve to configure

each macrocell, and the Connection Matrix which routes signals between macrocells. The third stage causes the reset of the input

pins, and then to enable them. After that, the LUTs are reset and become active. After LUTs the Delay cells, RC OSC, DFFs,

Latches and Pipe Delay are initialized. Only after all macrocells are initialized internal POR signal (POR macrocell output) goes

from LOW to HIGH. The last portion of the device to be initialized are the output PINs, which transition from high impedience to

active at this point.

The typical time that takes to complete the POR sequence varies by device type in the GreenPAK family. It also depends on many

environmental factors, such as: slew rate, VDD value, temperature and even will vary from chip to chip (process influence).

Figure 43. POR sequence

VDD

POR_NVM

(reset for NVM)

NVM_ready_out

POR_GPI

(reset for input enable)

POR_LUT

(reset for LUT output)

POR_CORE

(reset for DLY/RC OSC/DFF

/Latch/Pipe DLY/other macrocells

POR_OUT

(generate low to high to matrix)

POR_GPO

(reset for output enable)

Tsu

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