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SLG46110V データシート(PDF) 12 Page - Dialog Semiconductor

部品番号 SLG46110V
部品情報  Data Communications Equipment
PDF  82 Pages
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SLG46110V データシート(HTML) 12 Page - Dialog Semiconductor

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Page 11 of 81
SLG46110
5.7 Typical Counter/Delay Offset Measurements
5.8 Expected Delays and Widths
Table 3. Typical Counter/Delay Offset Measurements.
Parameter
RC OSC
Freq
RC OSC Power
VDD = 1.8 V VDD = 3.3V VDD = 5.0V
Unit
offset
25kHz
auto
19
14
12
s
offset
2MHz
auto
7
4
4
s
frequency settling time
25kHz
auto
19
14
12
s
frequency settling time
2MHz
auto
14
14
14
s
variable (CLK period)
25kHz
forced
0-40
0-40
0-40
s
variable (CLK period)
2MHz
forced
0-0.5
0-0.5
0-0.5
s
tpd (non-delayed edge)
25kHz/2MHz
either
35
14
10
ns
Table 4. Expected Delays and Widths for Programmable Delay (typical).
Symbol
Parameter
Note
VDD = 1.8 V VDD = 3.3V VDD = 5.0V
Unit
time1
Width, 1 cell
PDLY mode:(any)edge detect, edge detect
output
272.4
128.8
97.5
ns
time1
Width, 2 cell
PDLY mode:(any)edge detect, edge detect
output
582.7
272.6
205.1
ns
time1
Width, 3 cell
PDLY mode:(any)edge detect, edge detect
output
893.4
416.6
312.9
ns
time1
Width, 4 cell
PDLY mode:(any)edge detect, edge detect
output
1203.4
560.6
420.9
ns
time2
Delay, 1 cell
PDLY mode:(any)edge detect, edge detect
output
39.3
15.7
10.9
ns
time2
Delay, 2 cell
PDLY mode:(any)edge detect, edge detect
output
39.3
15.7
10.9
ns
time2
Delay, 3 cell
PDLY mode:(any)edge detect, edge detect
output
39.3
15.7
10.9
ns
time2
Delay, 4 cell
PDLY mode:(any)edge detect, edge detect
output
39.3
15.7
10.9
ns
time1
Delay, 1 cell
PDLY mode: both edge delay (shared
macrocell inputs)
354
161.5
120.1
ns
time1
Delay, 2 cell
PDLY mode: both edge delay (shared
macrocell inputs)
664.2
305.2
227.8
ns
time1
Delay, 3 cell
PDLY mode: both edge delay (shared
macrocell inputs)
974.9
449.1
335.7
ns
time1
Delay, 4 cell
PDLY mode: both edge delay (shared
macrocell inputs)
1284.8
593.1
443.6
ns
time1
Width
CNT3/DLY3 Rising Edge Detect (shared
macrocell inputs)
63.6
32.4
22.9
ns
time1
Width
CNT3/DLY3 Falling Edge Detect (shared
macrocell inputs)
61.3
31.1
22.5
ns
time1
Width
CNT3/DLY3 Both Edge Detect (shared
macrocell inputs)
62.2
31.6
22.7
ns



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