SLG46110V datasheet(37/82 Pages) DIALOG

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000-0046110-106

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SLG46110

10.3 3-Bit LUT or Pipe Delay Macrocell

There is one macrocell that can serve as either a 3-bit LUT or as a Pipe Delay.

When used to implement LUT functions, the 3-bit LUT take in three input signals from the connection matrix and produces a single

output, which goes back into the connection matrix.

When used as an 8-stage pipe delay, there are three inputs signals from the matrix, Input (IN), Clock (CK) and Reset (nReset).

The pipe delay cell is built from D Flip-Flop logic cells that provide the three delay options, two of which are user selectable. The

DFF cells are tied in series where the output (Q) of each delay cell goes to the next DFF cell. The two outputs (OUT0 and OUT1)

provide user selectable options for 1 to 8 stages of delay There are delay output points for each set of the OUT0 and OUT1 outputs

to a 3-input mux that is controlled by reg <666:663> for OUT0 and reg <670:667> for OUT1. The 3-input mux is used to control

the selection of the amount of delay.

The overall time of the delay is based on the clock used in the SLG46110 design. Each DFF cell has a time delay of the inverse

of the clock time (either external clock or the RC Oscillator within the SLG46110). The sum of the number of DFF cells used will

be the total time delay of the Pipe Delay logic cell.

Figure 13. 3-bit LUT4 or Pipe Delay

3-bit LUT4 OUT

IN1

IN0

reg <281:274>

From Connection

Matrix Output <24>

From Connection

Matrix Output <25>

IN2

From Connection

Matrix Output <26>

8 Flip-Flops

nReset

From Connection

Matrix Output <25>

From Connection

Matrix Output <24>

From Connection

Matrix Output <26>

reg <276:274>

reg <279:277>

To Connection

Matrix Input<14>

OUT1

OUT0

reg <432>

To Connection

Matrix Input<13>

reg <284>

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