peaking in its output impedance characteristic at

signal frequencies or their harmonics.

A large capacitor connected between VREF and

AGND can provide sufficiently low output im-

pedance at the high end of the frequency

spectrum, while almost all precision references

exhibit extremely low output impedance at dc.

The magnitude of the current load on the external

reference circuitry will scale to the CLKIN fre-

quency. At full speed, the reference must supply a

maximum load current of 10

(1

pedance of 15

Ω will therefore yield a maximum

error of 150 mV. With a 2.5V reference and LSB

size of 600 mV, this would insure better than 1/4

LSB accuracy. A 1

pedance of less than 15

Ω at frequencies greater

than 10 kHz. Similarly, for the CS5014 with a

4.5V reference (275

µV/LSB), better than

1/4 LSB accuracy can be insured with an output

impedance of 4

Ω or less (maximum error of

40

µV). A 2.2 µF capacitor exhibits an imped-

ance of less than 4

Ω at frequencies greater than

5kHz. For the CS5016 with a 4.5V reference

(69

µV/LSB), better than 1/4 LSB accuracy can

be insured with an output impedance of less than

2

Ω (maximum error of 20 µV). A 20 µF capaci-

tor exhibits an impedance of less than 2

Ω at

frequencies greater than 16 kHz. A high-quality

tantalum capacitor in parallel with a smaller ce-

ramic capacitor is recommended.

CLKIN

EOC

Status

EOT

HOLD

SCLK

SDATA

t

d

t

d

Determined

LSB

Fine Charge

Determined

MSB

Determined

MSB - 1

Determined

MSB - 2

Coarse Charge

LSB+1

LSB

MSB

MSB - 1

LSB+2

2

4

6

8

10

12

64

62

60

80/0

76

78

74

72

70

68

66

CS5016:

2

4

6

8

10

12

56

54

72/0

68

70

66

64

62

60

58

52

CS5014:

2

4

6

8

10

12

48

46

44

64/0

60

62

58

56

54

52

50

CS5012A:

Figure 9. Serial Output Timing

Notes: 1. Synchronous (loopback) mode is illustrated. After EOC falls the converter goes into coarse charge mode for

6 CLKIN cycles, then to fine charge mode for 9 cycles, then EOT falls. In loopback mode, EOT trips HOLD

which captures the analog sample. Conversion begins on the next rising edge of CLKIN. If operated asynchro-

nously, EOT will remain low until after HOLD is taken low. When HOLD occurs the analog sample is captured

immediately, but conversion may not begin until four CLKIN cycles later. EOT will return high

when conversion begins.

and over

± 10% supply variation

3. EOC returns high in 4 CLKIN cycles if A0 = 1 and CS = RD = 0 (Microprocessor Independent Mode);

within 4 CLKIN cycles after a data read (Microprocessor Mode); or 4 CLKIN cycles after HOLD = 0

is recognized on a rising edge of CLKIN/4.

CS5012A, CS5014, CS5016

DS14F8

2-25

CS5012A CS5014 CS5016

DS14F9

19