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CS5014 データシート(PDF) 34 Page - Cirrus Logic |
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CS5014 データシート(HTML) 34 Page - Cirrus Logic |
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34 / 40 page ![]() PIN DESCRIPTIONS Power Supply Connections VD+ – Positive Digital Power, PIN 1 2. Positive digital power supply. Nominally +5 volts. VD- – Negative Digital Power, PIN 40. Negative digital power supply. Nominally -5 volts. DGND – Digital Ground, PIN 1 1. Digital ground. VA+ – Positive Analog Power, PIN 28. Positive analog power supply. Nominally +5 volts. VA- – Negative Analog Power, PIN 34. Negative analog power supply. Nominally -5 volts. AGND – Analog Ground, PIN 30. Analog ground. Oscillator CLKIN – Clock Input, PIN 23. All conversions and calibrations are timed from a master clock which can either be supplied by driving this pin with an external clock signal, or can be internally generated by tying this pin to DGND. Digital Inputs HOLD – Hold, PIN 1. A falling transition on this pin sets the CS5012A/14/16 to the hold state and initiates a conversion. This input must remain low at least one CLKIN cycle plus 50 ns. CS – Chip Select, PIN 24. When high, the data bus outputs are held in a high impedance state and the input to CAL and INTRLV are ignored. A falling transition initiates or terminates burst or interleave calibration (depending on the status of CAL and INTRLV) and a rising transition latches both the CAL and INTRLV inputs. If RD is low, the data bus is driven as indicated by BW and A0. RD – Read, PIN 25. When RD and CS are both low, data is driven onto the data bus. If either signal is high, the data bus outputs are held in a high impedance state. The data driven onto the bus is determined by BW and A0. CS5012A, CS5014, CS5016 DS14F8 2-41 CS5012A CS5014 CS5016 34 DS14F9 |
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