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CS5014 データシート(PDF) 32 Page - Cirrus Logic

部品番号 CS5014
部品情報  16,14 & 12-BIT SELF CALIBRATING A/D CONVERTERS
PDF  40 Pages
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メーカー  CIRRUS [Cirrus Logic]
ホームページ  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

CS5014 データシート(HTML) 32 Page - Cirrus Logic

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Figure 36. CS5012A/14/16 System Connection Diagram
29
31
32
34
28
30
12
11
40
VREF
AIN
REFBUF
VA-
AGND
VA+
VD+
DGND
VD-
+5V
-5V
10
Ω
10
Ω
Voltage
Reference
Reset
Generator
Data
Processor
Serial
Data
Interface
(optional)
Clock
Source
(optional)
Control
Logic
Mode
Select *
Analog
Supply
Source
Signal
Analog
Supply
Analog
TST
BW
RESET
A0
CAL
D0-D15
SCLK
SDATA
CLKIN
27
37
23
44
43
8 or 16
42
41
1
39
38
24
25
26
36
35
0.1
µF
0.01
µF
0.1
µF
0.1
µF
May be
microprocessor
or discrete logic.
0.1
µF
INTRLV
EOC
EOT
HOLD
BP/UP
RD
CS
0.1
µF
CS5012A
or
VREF
±VREF
0
10 µF
Signal
Conditioning
1000 pF
200
Ω
CS5014
CS5016
Unused Logic inputs should only
be connected to VD+ or DGND.
* BW and BP/UP should always
be terminated to VD+ or DGND,
For best dynamic
S/(N+D) performance.
or driven by a logic gate.
Function
RST
A0
CAL
Hold and Start Convert
Initiate Burst Calibration
Stop Burst Cal and Begin Track
Initiate Interleave Calibration
Terminate Interleave Cal
Read Output Data
Read Status Register
High Impedance Data Bus
High Impedance Data Bus
Reset
Reset
0
0
0
0
0
0
0
X
X
1
X
*
*
*
*
*
1
0
*
*
X
0
X
X
X
X
X
0
0
X
1
X
X
X
X
X
0
1
X
X
X
X
X
X
X
1
0
X
X
X
X
X
X
X
X
X
0
0
0
0
0
0
1
X
X
0
X
1
X
X
X
1
X
X
X
0
HOLD
CS
INTRLV
RD
Table 4. CS5012A/14/16 Truth Table
*
The status of A0 is not critical to the operation specified. However, A0 should not be low with
CS and HOLD low, or a software reset will result.
CS5012A, CS5014, CS5016
DS14F8
2-39
CS5012A CS5014 CS5016
32
DS14F9



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