CS5014 datasheet(20/40 Pages) CIRRUS

20 / 40 page

Peaking in the reference’s output impedance can

occur because of capacitive loading at its output.

Any peaking that might occur can be reduced by

placing a small resistor in series with the capaci-

tors (Figure 10). The equation in Figure 10 can

be used to help calculate the optimum value of R

for a particular reference. The term "fpeak" is the

frequency of the peak in the output impedance of

the reference before the resistor is added.

The CS5012A/14/16 can operate with a wide

range of reference voltages, but signal-to-noise

performance is maximized by using as wide a

signal range as possible. The recommended refer-

ence voltage is between 2.5 and 4.5 V for the

CS5012A and 4.5 V for the CS5014/16. The

CS5012A/14/16 can actually accept reference

voltages up to the positive analog supply. How-

ever, the buffer’s offset may increase as the

reference voltage approaches VA+ thereby in-

creasing external drive requirements at VREF. A

4.5V reference is the maximum reference voltage

recommended. This allows 0.5V headroom for

the internal reference buffer. Also, the buffer en-

lists the aid of an external 0.1

µF ceramic

capacitor which must be tied between its output,

REFBUF, and the negative analog supply, VA-. For

more information on references, consult the applica-

tion note: Voltage References for the CS501X Se-

ries of A/D Converters. For an example of using

the CS5012A/14/16 with a 5 volt reference, see

the application note: A Collection of Application

Hints for the CS501X Series of A/D Converters.

Analog Input Connection

The analog input terminal functions similarly to

the VREF input after each conversion when

switching into the track mode. During the first

six CLKIN cycles in the track mode, the buffered

version of the analog input is used for pre-charg-

ing the capacitor array. An additional period is

required for fine-charging directly from AIN to

VREF

REFBUF

VA-

0.1 µF

-5V

ref

1.0

µF

0.01

µF

+Vee

CS5012A

CS5014

CS5016

π (C1 + C2) fpeak

Figure 10. Reference Connections

Fine-Charge

Pre-Charge

Acquisition Time (us)

0.5

1.0

1.5

2.0

2.5

(Delay from EOC)

+12.5

-12.5

-25.0

+50

-50

-100

+200

-200

-400

CS5012A

CS5014

CS5016

Figure 11. Internal Acquisition Time

CS5012A, CS5014, CS5016

2-26

DS14F8

CS5012A CS5014 CS5016

DS14F9

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