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XRT83SL34 データシート(PDF) 43 Page - Exar Corporation

部品番号 XRT83SL34
部品情報  QUAD T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
PDF  80 Pages
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メーカー  EXAR [Exar Corporation]
ホームページ  http://www.exar.com
Logo EXAR - Exar Corporation

XRT83SL34 データシート(HTML) 43 Page - Exar Corporation

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XRT83SL34
QUAD T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
PRELIMINARY
REV. P1.0.8
40
DUAL LOOP-BACK
Figure 22 depicts the data flow in dual-loopback. In this mode, selecting the jitter attenuator in the transmit path
will have the same result as placing the jitter attenuator in the receive path. In dual Loop-Back mode the
recovered clock and data from the line are looped back through the transmitter to the TTIP and TRING without
passing through the jitter attenuator. The transmit clock and data are looped back through the jitter attenuator
to the RCLK and RPOS/RDATA and RNEG pins.
FIGURE 22. SIGNAL FLOW IN DUAL LOOP-BACK MODE
Tx
Decoder
Timing
Control
Rx
Data &
Clock
Recovery
JA
TPOS
TNEG
TCLK
RCLK
RPOS
RNEG
Encoder
TTIP
TRING
RTIP
RRING



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