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XRT83SL34 データシート(PDF) 58 Page - Exar Corporation |
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XRT83SL34 データシート(HTML) 58 Page - Exar Corporation |
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58 / 80 page  XRT83SL34 QUAD T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. P1.0.8 PRELIMINARY 55 TABLE 25: MICROPROCESSOR REGISTER #6, BIT DESCRIPTION REGISTER ADDRESS 0000110 0010110 0100110 0110110 CHANNEL_n CHANNEL_0 CHANNEL_1 CHANNEL_2 CHANNEL_3 FUNCTION REGISTER TYPE RESET VALUE BIT #NAME D7 Reserved RO 0 D6 DMOIS_n Driver Monitor Output Interrupt Status: This bit is set to a “1” every time the DMO status has changed since last read. NOTE: This bit is reset upon read. RUR 0 D5 FLSIS_n FIFO Limit Interrupt Status: This bit is set to a “1” every time when FIFO Limit (Read/Write pointer with +/- 3 bits apart) sta- tus has changed since last read. NOTE: This bit is reset upon read. RUR 0 D4 LCVIS_n Line Code Violation Interrupt Status: This bit is set to a “1” every time when LCV status has changed since last read. NOTE: This bit is reset upon read. RUR 0 D3 NLCDIS_n Network Loop-Code Detection Interrupt Status: This bit is set to a “1” every time when NLCD status has changed since last read. NOTE: This bit is reset upon read. RUR 0 D2 AISDIS_n AIS Detection Interrupt Status: This bit is set to a “1” every time when AISD status has changed since last read. NOTE: This bit is reset upon read. RUR 0 D1 RLOSIS_n Receive Loss of Signal Interrupt Status: This bit is set to a “1” every time RLOS status has changed since last read. NOTE: This bit is reset upon read. RUR 0 D0 QRPDIS_n Quasi-Random Pattern Detection Interrupt Status: This bit is set to a “1” every time when QRPD status has changed since last read. NOTE: This bit is reset upon read. RUR 0 |
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