XRT83SL34 datasheet(76/80 Pages) EXAR

部品番号	XRT83SL34

部品情報	QUAD T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

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XRT83SL34

QUAD T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

REV. P1.0.8

PRELIMINARY

MICROPROCESSOR INTERFACE I/O TIMING

INTEL INTERFACE TIMING - ASYNCHRONOUS

The signals used for the Intel microprocessor interface are: Address Latch Enable (ALE), Read Enable (RD),

Write Enable (WR), Chip Select (CS), Address and Data bits. The microprocessor interface uses minimum ex-

ternal glue logic and is compatible with the timings of the 8051 or 80C188 with an 8-16 MHz clock frequency,

and with the timings of x86 or i960 family or microprocessors. The interface timing shown in Figure 28 and

Figure 30 is described in Table 49.

FIGURE 27. RECEIVE CLOCK AND OUTPUT DATA TIMING

FIGURE 28. INTEL ASYNCHRONOUS PROGRAMMED I/O INTERFACE TIMING

RCLK

RPOS

RNEG

A DDR[6:0]

DA T A [7 :0]

RD_D S

WR _R /W

RD Y _ DT A C K

V alid D ata for R ead ba ck

D ata A v aila ble to W rite In to th e LIU

READ O P ERAT IO N

W RIT E O P E RAT IO N

V a lid A ddres s

V alid A d dre s s

ALE_AS

XRT83SL34 データシート(PDF) 76 Page - Exar Corporation