AD9546SLASHPCBZ datasheet(134/205 Pages) AD

134 / 205 page

AD9546

Data Sheet

Rev. 0 | Page 134 of 205

PHASE SLEW RATE LIMIT

The digital phase detector uses the reference and feedback

TDCs to determine the associated phase error and pass the

error along to the loop filter. In addition to the loop phase

error, however, other types of phase information can appear in

the loop, for example, phase offsets originating from any of the

following:



Changes to the DPLL phase offset (see the DPLL Phase

Offset Control section)



Changes to the phase skew offset (see the Source Profiles

section)



From the delay compensation block (see the Delay

Compensation section)



As the result of a phase buildout operation (see the Phase

Buildout Mode section)

For certain phase sources, the DPLL provides a phase slew rate

limiting function (see Figure 96) that places an upper bound on

the rate of change of phase passed along to the loop filter. The

phase slew rate limiter mitigates the adverse effects of injecting

a large phase step into the loop by converting the phase step to

a phase ramp with the maximum slope set by the user.

The phase slew rate limiter operates only on phase transients

introduced by the following phase sources:



DPLL phase offset (see the DPLL Phase Offset Control

section)



Phase skew offset (see the Source Profiles section)



Initial phase correction due to activating a hitless mode

translation profile (see the Translation Modes section)

That is, the DPLL only applies phase slew limiting under two

conditions. The first is a phase offset that exists at the start of a

reference acquisition. The second is phase offsets introduced by

the user via the DPLL phase offset feature and the phase skew

offset feature.

To set the phase slew limit rate, use Bits[31:0] (unsigned) in

the phase slew limit value. The DPLL phase slew limit value has

units of ps/sec or 10−12, but accuracy is typically limited to

approximately 50 ps/sec.

The phase slew rate limit feature is active for all DPLL phase

slew limit values except zero, which disables the phase slew rate

limiter (disabling the phase slew rate limiter is not recommended).

However, there is little reason to disable the rate limiter. Instead,

programming the rate limiter to the maximum value imposes a

slew rate limit corresponding to a frequency shift in excess of

4000 ppm. Most applications do not experience frequency

transients exceeding 4000 ppm. The DPLL phase slew limit default

value establishes a phase slew rate limit of 100,663,296 ps/sec

(which equates to a maximum frequency shift of approximately

100 ppm).

The relationship between the desired phase slew rate limit, Δt/t,

and the value of the DPLL phase slew limit value is as follows:

DPLL Phase Slew Limit Value = (Δt/t) × 1012

For example, given a desired upper bound to the rate of change

of phase (Δt/t) of 0.25 ppm (2.5 × 10−7), find the required DPLL

phase slew limit value as follows:

DPLL Phase Slew Limit Value = (Δt/t) × 1012

= (2.5 × 10−7) × 1012

= 250,000

= 0x 0003 D090 (hexadecimal)

When the phase slew limiter is actively limiting the rate of

change of phase, status Bit 2 (DPLL phase slew limiting) is

Logic 1 of Register 0x3102 (for DPLL0) or Register 0x3202 (for

DPLL1). Bit 2 relates to the IRQ function (see the Interrupt

Request (IRQ) section) through Bit 4 (DPLL phase slew limiter

active) and D5 (DPLL phase slew limiter inactive) in Register

0x3010 (for DPLL0) and Register 0x3015 (for DPLL1). Because

Bit 4 and Bit 5 are latched, the user must use Bit 4 and Bit 5,

respectively, of Register 0x200B (for DPLL0) and Register

0x2010 (for DPLL1) to clear the latched state. Otherwise, the user

cannot observe subsequent state transitions of Bit 2.

DIGITAL

PHASE

DETECTOR

DIGITAL

LOOP

FILTER

SYSTEM

CLOCK

NUMERIC

COEFFICIENTS

NCO

LOCK

DETECTORS

FTW

PROCESSOR

LOOP

CONTROLLER

XOA XOB

AD9546

TDC

48-BIT

FTW

FREERUN TUNING WORD

DIGITAL CROSS

POINT MUX

NOTES

1. A RANGE OF BITS USES A COLON SEPARATOR

2. REGISTER ADDRESSES ARE SPECIFIC TO DPLL0

N DIVIDER

REG 0x1005 TO 0x1000, BITS[45:0]

REG 0x1014 TO 0x1011, BITS[31:0]

Figure 96. Phase Slew Rate Limit Feature

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