AD9546SLASHPCBZ datasheet(137/205 Pages) AD

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Data Sheet

AD9546

Rev. 0 | Page 137 of 205

mechanism for knowing when the tuning word history

processor refreshes the DPLL tuning word history. However,

the DPLL history updated bit is a latched bit. Therefore, this bit

indicates a refresh of the DPLL tuning word history, but not

necessarily the most recent history.

DPLL Clear History Bit

The user can clear the averaging history at any time via Bit 1 of

Logic 1 forces the averaging processor to clear the averaging

circuitry, thereby erasing any previous tuning word history

information, and forces the DPLL history available bit to

Logic 0 (until a newly computed initial average is available).

Programming the DPLL clear history bit to Logic 1 does not

clear the contents of the DPLL tuning word history. That is, the

last update of the DPLL tuning word history remains intact

until the processor calculates a new average and sets the DPLL

history updated bit, thereby notifying the user a new average is

available.

DPLL Single Sample History Bit

When the DPLL must make a switch from active closed-loop

operation to holdover operation, it attempts to use the tuning

word history from the averaging processor. However, if the

averaging processor has not yet set the DPLL history available

status bit (indicating no history is available), the DPLL uses the

DPLL freerun tuning word as the tuning word for the NCO by

default. Alternatively, the user can have the DPLL use the most

recent tuning word from the loop filter instead. To use the most

recent tuning word from the loop filter, program Bit 1 to Logic

1 of Register 0x100E (for DPLL0) and Register 0x140E (for

DPLL1).

DPLL Quick Start History Bit

Normally, when the DPLL is in active closed-loop operation,

the averaging processor must process tuning words for at least

the amount of time prescribed by the DPLL history accumulation

timer. The prescribed time is necessary to compute a full tuning

word history average and to set the DPLL history available bit

(thereby indicating the averaging processor has processed

enough tuning words to compute an initial average). However,

the user has the option to allow the averaging processor to

indicate the history is available earlier by writing a Logic 1 to

Bit 2 of Register 0x100E (for DPLL0) and Register 0x140E (for

DPLL1). Under this condition, the averaging processor sets the

DPLL history available status bit after the first two subintervals

expire and updates the DPLL tuning word history. Updates of

the DPLL tuning word history continue every subinterval

thereafter.

During the first eight subintervals of the quick start history

sequence, the second and third subintervals exhibit a two-

subinterval averaging window. The fourth, fifth, sixth, and

seventh subintervals exhibit a four-subinterval averaging

window. Finally, the eighth subinterval exhibits an eight-

subinterval averaging window, which remains the case for all

subsequent subintervals.

The quick start feature is useful when the time span dictated by

the DPLL history accumulation timer is very large (hours, for

example). The quick start feature allows the averaging

processor to make an initial tuning word average available after

¼ of the time indicated by the DPLL history accumulation timer.

The DPLL single sample history and DPLL quick start history

bits are not mutually exclusive. Both can be set to provide both

options simultaneously with the state of the averaging

processor, dictating which option is applicable for the

prevailing conditions. Following a switch from active closed-

loop operation to holdover operation, the progress made by the

averaging processor in computing the initial tuning word

average directs the action of the tuning word processor

according to the state of the DPLL single sample history bit and

the DPLL quick start history bit.

DPLL Persistent History Bit

The DPLL persistent history bit works in conjunction with the

control bits described in the Averaging Processor Continue or

Reset section. The DPLL persistent history bit is Bit 0 of

When Bit 0 = 0, the tuning word processor resets the averaging

processor based on the control bits described in the Averaging

Processor Continue or Reset section. When Bit 0 = 1, this

setting prevents the tuning word processor from clearing the

averaging processor based on the control bits described in the

Averaging Processor Continue or Reset section. Instead, the

averaging processor holds onto the previous computation. That

is, the computation pauses or persists.

Averaging Processor Continue or Reset

By default, the averaging processor continues to compute a

rolling average regardless of the state of the DPLL. The following

three bits provide optional control over resetting or pausing the

averaging processor based on the DPLL state:

•

DPLL pause history while phase unlocked

•

DPLL pause history while frequency unlocked

•

DPLL pause history while phase slew limiting

These bits pause or reset the averaging process depending on

the DPLL persistent history bit. When DPLL persistent history = 0,

these three bits cause the averaging processor to reset. When

DPLL persistent history = 1, these three bits cause the averaging

processor to pause and then resume when the conditions

dictate.

The DPLL pause history while phase unlocked bit is Bit 0 of

Programming Bit 0 = 1 pauses or resets the averaging processor

while the DPLL is not phase locked.

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