AD9546SLASHPCBZ datasheet(138/205 Pages) AD

138 / 205 page

AD9546

Data Sheet

Rev. 0 | Page 138 of 205

The DPLL pause history while frequency unlocked bit is Bit 1

of Register 0x100F (for DPLL0) and Register 0x140F (for

DPLL1). Programming Bit 1 = 1 pauses or resets the averaging

processor while the DPLL is not frequency locked.

The DPLL pause history while phase slew limiting bit is Bit 2 of

Programming Bit 2 = 1 pauses or resets the averaging processor

while the phase slew limiter is slew limiting (see the Phase Slew

Rate Limit section).

The user can set any combination of these bits. Unlike the

averaging processor delay bits, however, when more than one

of these bits are Logic 1, the implementation of the delay

behaves as an OR function of the selected conditions. That is,

satisfying any of the selected status conditions causes the

averaging processor to reset or pause.

DELAY COMPENSATION

Overview

Delay compensation provides an automatic phase offset to the

DPLL to counteract temperature dependent delay variation.

Figure 97 is a block diagram of the DPLL and delay compensation

block. Delay compensation is only in effect while the DPLL is

active. Furthermore, the response time of the delay

compensation at the DPLL output is subject to the loop

bandwidth of the DPLL.

Delay compensation generates the temperature dependent time

offset value, Δt, based on a fifth degree polynomial, as shown in

Figure 97. The independent variable of the polynomial is

temperature (T in Figure 97). The five polynomial coefficients

(C1 to C5), which the user enters via the register map, scale with

corresponding powers of T. Note that there is no need for a

constant term (C0) in the delay compensation block, because the

DPLL phase offset feature (see the DPLL Phase Offset Control

section) provides that function. The Δt computation implied by

Figure 97 is

∆=

∑

The temperature (T) input into the open-loop direct compensation

block originates from temperature sensor circuitry (see the

Temperature Sensor section). The user has the option of choosing

the temperature source: either the internal temperature sensor

(default) or a user supplied temperature via the register map.

When using the internal temperature sensor, the device

inherently uses the appropriate scaling units. However, when

using the register map option, the user must provide the proper

scaling (see the External Temperature Source section for

details).

DIGITAL

PHASE

DETECTOR

DIGITAL

LOOP

FILTER

DPLL0 PHASE

OFFSET

SYSTEM

CLOCK

NUMERIC

COEFFICIENTS

NCO

LOCK

DETECTORS

FTW

PROCESSOR

LOOP

CONTROLLER

XOA XOB

AD9546

TDC

48-BIT

FTW

FREERUN TUNING WORD

NOTES

1. A RANGE OF BITS USES A COLON SEPARATOR

2. REGISTER ADDRESSES ARE SPECIFIC TO DPLL0

N DIVIDER

FILTER

DELAY COMPENSATION

Δt

TDC

REG 0x1029, BITS[2:0]

REG 0x1019 TO 0x1015, BITS[39:0]

REG 0x1005 TO 0x1000, BITS[45:0]

Figure 97. Delay Compensation

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