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AD9546/PCBZ データシート(PDF) 197 Page - Analog Devices

部品番号 AD9546/PCBZ
部品情報  Dual DPLL Digitized Clock Synchronizer
PDF  205 Pages
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メーカー  AD [Analog Devices]
ホームページ  http://www.analog.com
Logo AD - Analog Devices

AD9546/PCBZ データシート(HTML) 197 Page - Analog Devices

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Data Sheet
AD9546
Rev. 0 | Page 197 of 205
CAL_COUNT =
CAL_COUNT + 1
CAL_COUNT = 0
VCO
CALIBRATION
OPERATION
CAL_COUNT > 1
NO
YES
SYSTEM CLOCK
RECALIBRATION LOOP
WRITE:
REGISTER 0x2000, BIT 2 = 0
WRITE:
REGISTER 0x000F = 0x01
WRITE:
REGISTER 0x000F = 0x01
WRITE:
REGISTER 0x2000, BIT 2 = 1
START TIMEOUT CLOCK:
TIME = 0
REGISTER 0x3001,
BITS[1:0] = 0x3
TIMEOUT CLOCK:
TIME > SYSCLK_TO1
YES
NO
YES
SYSTEM CLOCK
LOCKED AND
STABLE POLLING LOOP
END
(TO RST_COUNT CHECK)
END
START
1SYSCLK_TO IS A TIMEOUT VALUE CALCULATED BY THE CONTROLLING SOFTWARE.
SYSCLK_TO = 50ms + SYSTEM CLOCK VALIDATION TIME (REGISTER 0x0207 TO REGISTER 0x0209 [UNITS OF ms])
Figure 133. System Clock Initialization Subprocess



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