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AD9546/PCBZ データシート(PDF) 198 Page - Analog Devices

部品番号 AD9546/PCBZ
部品情報  Dual DPLL Digitized Clock Synchronizer
PDF  205 Pages
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メーカー  AD [Analog Devices]
ホームページ  http://www.analog.com
Logo AD - Analog Devices

AD9546/PCBZ データシート(HTML) 198 Page - Analog Devices

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AD9546
Data Sheet
Rev. 0 | Page 198 of 205
START TIMEOUT CLOCK:
TIME = 0
CAL_COUNT = 0
LOCK REGISTER, BIT 3 = 1
TIMEOUT CLOCK:
TIME > 50ms
CAL_COUNT > 1
NO
YES
NO
YES
NO
YES
CAL_COUNT =
CAL_COUNT + 1
APLL LOCK DETECT
POLLING LOOP
START
END
END
(TO RST_COUNT
CHECK)
WRITE:
REGISTER 0x0F, BIT 0 = 1
WRITE:
CAL REGISTER, BIT 1 = 1
WRITE:
SYNC REGISTER, BIT 3 = 1
WRITE:
REGISTER 0x0F, BIT 0 = 1
WRITE:
REGISTER 0x0F, BIT 0 = 1
MANUAL DISTRIBUTION
SYNCHRONIZATION
OPERATION
WRITE:
SYNC REGISTER, BIT 3 = 0
AUTOSYNC
REGISTERS, BITS[1:0] = 0
NO
YES
VCO
CALIBRATION
OPERATION
WRITE:
CAL REGISTER, BIT 1 = 0
WRITE:
REGISTER 0x0F, BIT 0 = 1
WRITE:
CAL REGISTER, BIT 1 = 0
WRITE:
REGISTER 0x0F, BIT 0 = 1
APLL RECALIBRATION
LOOP
REGISTER
0x2100
0x2200
APLL
0
1
REGISTER
0x3100
0x3200
REGISTER
0x2101
0x2201
REGISTER
0x10DB
0x14DB
Figure 134. APLL Initialization Subprocess



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