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データシートサーチシステム |
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データシートサーチシステム |
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AD9546/PCBZ データシート(PDF) 201 Page - Analog Devices |
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AD9546/PCBZ データシート(HTML) 201 Page - Analog Devices |
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201 / 205 page  Data Sheet AD9546 Rev. 0 | Page 201 of 205 CSB SCLK SDIO SDO REGISTER (N) DATA 16-BIT INSTRUCTION HEADER REGISTER (N – 1) DATA REGISTER (N – 2) DATA REGISTER (N – 3) DATA A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 DON'T CARE DON'T CARE DON'T CARE DON'T CARE D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 Figure 136. Serial Control Port Read—MSB First, Address Decrement, Four Bytes of Data tS DON'T CARE DON'T CARE A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 D4 D3 D2 D1 D0 DON'T CARE DON'T CARE R/W tDS tDH tHIGH tLOW tCLK tC CSB SCLK SDIO Figure 137. Timing Diagram for Serial Control Port Write—MSB First DATA BIT N – 1 DATA BIT N CSB SCLK SDIO SDO tDV Figure 138. Timing Diagram for Serial Control Port Register Read—MSB First CSB SCLK DON'T CARE DON'T CARE 16-BIT INSTRUCTION HEADER REGISTER (N) DATA REGISTER (N + 1) DATA SDIO DON'T CARE DON'T CARE A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 D1 D0 R/W A14 A13 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 Figure 139. Serial Control Port Write—LSB First, Address Increment, Two Bytes of Data CSB SCLK SDIO tHIGH tLOW tCLK tS tDS tDH tC BIT N BIT N + 1 Figure 140. Serial Control Port Timing—Write Table 114. Serial Control Port Timing Parameter Description tDS Setup time between data and the rising edge of SCLK tDH Hold time between data and the rising edge of SCLK tCLK Period of the clock tS Setup time between the CSB falling edge and the SCLK rising edge (start of the communication cycle) tC Setup time between the SCLK rising edge and CSB rising edge (end of the communication cycle) tHIGH Minimum period that SCLK is in a logic high state tLOW Minimum period that SCLK is in a logic low state tDV SCLK to valid SDIO (see Figure 138) |
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