AD9546SLASHPCBZ datasheet(200/205 Pages) AD

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AD9546

Data Sheet

Rev. 0 | Page 200 of 205

To make the buffer register data effective, the user must

perform an IO update operation, which transfers the contents

of all buffer registers to the active registers. The output of the

active registers causes the desired effect upon the functional

blocks within the device.

There are two methods available for issuing an IO update

operation:

1. Writing Logic 1 to Bit 0 of Register 0x000F

2. Configuring an Mx pin as a physical IO update pin

In the case of the first method, Bit 0 is an autoclearing bit. In

the case of the second method, applying Logic 1 to the

configured Mx pin asserts the IO update operation.

The user can program as many register bits as desired before

executing the IO update operation. Then, upon assertion of the

IO update operation, the all the buffer register contents transfer

to their active register counterparts.

Write

When the instruction word indicates a write operation, the

payload is written into the serial control port buffer of the

AD9546. Data bits are registered on the rising edge of SCLK.

Generally, it does not matter what data is written to blank

registers. However, it is customary to use 0s. The user must

verify that all reserved registers within a specific range have a

default value of 0x00. However, Analog Devices makes every

effort to avoid having reserved registers with nonzero default

values.

Read

If the instruction word indicates a read operation, the next

N × 8 SCLK cycles clock out the data starting from the address

specified in the instruction word, where N is the number of

data bytes to read. Read data appears on the appropriate data

pin (SDIO or SDO) on the falling edge of SCLK. The user must

latch the read data on the rising edge of SCLK. The internal SPI

control logic does not skip over blank registers during a

readback operation.

A readback operation takes data from either the serial control

port buffer registers or the active registers, as determined by

SPI Instruction Word (16 Bits)

The MSB of the 16-bit instruction word is R/W, which

indicates whether the ensuing operation is read or write. The

next 15 bits are the register address (A14 to A0), which indicates

the starting register address of the read/write operation (see

Table 113). The SPI controller ignores A14, treating it as Logic 0,

because the AD9546 has no register addresses requiring more

than a 14-bit address word.

SPI MSB First and LSB First Transfers

The AD9546 instruction word and payload can be transferred

MSB first or LSB first. The default for the AD9546 is MSB first.

To invoke LSB first mode, write a Logic 1 to Register 0x0000,

Bit 6. Immediately after invoking LSB first mode, subsequent

serial control port operations are LSB first.

Address Ascension

If the address ascension bit (Register 0x0000, Bit 5) is Logic 0,

serial control port register addressing decrements from the

specified starting address toward Address 0x0000. If the address

ascension bit (Register 0x0000, Bit 5) is Logic 1, serial control

port register addressing increments from the starting address

toward Address 0x3A3B. Reserved addresses are not skipped

during multibyte input/output operations. Therefore, write the

default value to a reserved register and Logic 0s to unmapped

registers. It is more efficient to issue a new write command

than to write the default value to more than two consecutive

reserved (or unmapped) registers.

Table 112. Streaming Mode (No Addresses Skipped)

Address Ascension

Stop Sequence

Increment

0x0000 to 0x3A3B

Decrement

0x3A3B to 0x0000

Table 113. Serial Control Port, 16-Bit Instruction Word

MSB

LSB

I15

I14

I13

I12

I11

I10

R/W

A14

A13

A12

A11

A10

CSB

SCLK DON'T CARE

SDIO

A12

A13

A14

R/W

A11 A10 A9

A6 A5

D2 D1

DON'T CARE

16-BIT INSTRUCTION HEADER

Figure 135. Serial Control Port Write—MSB First, Address Decrement, Two Bytes of Data

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